/**
 @file sys_usw_register.c

 @date 2009-11-6

 @version v2.0


*/

/****************************************************************
 *
 * Header Files
 *
 ***************************************************************/
#include "ctc_error.h"
#include "ctc_warmboot.h"
#include "ctc_packet.h"
#include "ctc_l2.h"
#include "ctc_pdu.h"
#include "ctc_diag.h"
#include "ctc_npm.h"
#include "sys_usw_common.h"
#include "sys_usw_register.h"
#include "sys_usw_ftm.h"
#include "sys_usw_parser.h"
#include "sys_usw_interrupt.h"
#include "ctc_register.h"
#include "sys_usw_dma.h"
#include "sys_usw_wb_common.h"
#include "sys_usw_opf.h"
#include "sys_usw_port_api.h"
#include "sys_usw_scl_api.h"
#include "sys_usw_mac.h"
#include "sys_usw_acl_api.h"
#include "sys_usw_srv6.h"
#include "sys_usw_diag.h"
#include "sys_usw_linkagg.h"
#include "sys_usw_npm.h"

#include "drv_api.h"
#include "usw/include/drv_ftm.h"
#include "sal_mutex.h"

#include "sys_usw_internal_port.h"
#include "usw/include/drv_common.h"

#define SYS_USW_L2L3_KEY_U2_MODE_MAX                      3
#define SYS_USW_L2L3_KEY_U3_MODE_MAX                      3
#define SYS_USW_MAC_IPV6_KEY_U0_MODE_MAX                  2
#define SYS_USW_MAC_IPV6_KEY_U1_MODE_MAX                  2

#define SYS_USW_IP_IM_NEXT_PROTOCOL_OFFSET_IPV4                3
#define SYS_USW_IP_IM_NEXT_PROTOCOL_OFFSET_IPV6                0
#define SYS_USW_IP_IM_HEADER_LENGTH_IPV4                  4
#define SYS_USW_IP_IM_HEADER_LENGTH_IPV6                  8

/*IPE Discard Type*/
#define IPEDISCARDTYPE_RESERVED0                          0x0
#define IPEDISCARDTYPE_LPBK_HDR_ADJ_RM_ERR                0x1
#define IPEDISCARDTYPE_PARSER_LEN_ERR                     0x2
#define IPEDISCARDTYPE_UC_TO_LAG_GROUP_NO_MEMBER          0x3
#define IPEDISCARDTYPE_EXCEP2_DIS                         0x4
#define IPEDISCARDTYPE_DS_USERID_DIS                      0x5
#define IPEDISCARDTYPE_RECEIVE_DIS                        0x6
#define IPEDISCARDTYPE_MICROFLOW_POLICING_FAIL_DROP       0x7
#define IPEDISCARDTYPE_SVC_POLICING_DIS                   0x7
#define IPEDISCARDTYPE_PROTOCOL_VLAN_DIS                  0x8
#define IPEDISCARDTYPE_AFT_DIS                            0x9
#define IPEDISCARDTYPE_L2_ILLEGAL_PKT_DIS                 0xa
#define IPEDISCARDTYPE_STP_DIS                            0xb
#define IPEDISCARDTYPE_DEST_MAP_PROFILE_DISCARD           0xc
#define IPEDISCARDTYPE_STACK_REFLECT_DISCARD              0xd
#define IPEDISCARDTYPE_ARP_DHCP_DIS                       0xe
#define IPEDISCARDTYPE_DS_PHYPORT_SRCDIS                  0xf
#define IPEDISCARDTYPE_VLAN_FILTER_DIS                    0x10
#define IPEDISCARDTYPE_DS_SCL_DIS                         0x11
#define IPEDISCARDTYPE_ROUTE_ERROR_PKT_DIS                0x12
#define IPEDISCARDTYPE_SECURITY_CHK_DIS                   0x13
#define IPEDISCARDTYPE_STORM_CTL_DIS                      0x14
#define IPEDISCARDTYPE_LEARNING_DIS                       0x15
#define IPEDISCARDTYPE_NO_FORWARDING_PTR                  0x16
#define IPEDISCARDTYPE_IS_DIS_FORWARDING_PTR              0x17
#define IPEDISCARDTYPE_FATAL_EXCEP_DIS                    0x18
#define IPEDISCARDTYPE_APS_DIS                            0x19
#define IPEDISCARDTYPE_DS_FWD_DESTID_DIS                  0x1a
#define IPEDISCARDTYPE_LOOPBACK_DIS                       0x1b
#define IPEDISCARDTYPE_DISCARD_PACKET_LOG_ALL_TYPE        0x1c
#define IPEDISCARDTYPE_PORT_MAC_CHECK_DIS                 0x1d
#define IPEDISCARDTYPE_L3_EXCEP_DIS                       0x1e
#define IPEDISCARDTYPE_STACKING_HDR_CHK_ERR               0x1f
#define IPEDISCARDTYPE_TUNNEL_DECAP_MARTIAN_ADD           0x20
#define IPEDISCARDTYPE_TUNNELID_FWD_PTR_DIS               0x21
#define IPEDISCARDTYPE_VXLAN_FLAG_CHK_ERROR_DISCARD       0x22
#define IPEDISCARDTYPE_VXLAN_NVGRE_INNER_VTAG_CHK_DIS     0x23
#define IPEDISCARDTYPE_VXLAN_NVGRE_CHK_FAIL               0x24
#define IPEDISCARDTYPE_GENEVE_PAKCET_DISCARD              0x25
#define IPEDISCARDTYPE_ICMP_REDIRECT_DIS                  0x26
#define IPEDISCARDTYPE_ICMP_ERR_MSG_DIS                   0x27
#define IPEDISCARDTYPE_PTP_PKT_DIS                        0x28
#define IPEDISCARDTYPE_MUX_PORT_ERR                       0x29
#define IPEDISCARDTYPE_HW_ERROR_DISCARD                   0x2a
#define IPEDISCARDTYPE_USERID_BINDING_DIS                 0x2b
#define IPEDISCARDTYPE_MACSEC_UNCONTROLLED_PORT_DIS       0x2c
#define IPEDISCARDTYPE_MPLS_ES_LABEL_CHK                  0x01    /*TMM*/

/*EPE Discard Type*/
#define EPEDISCARDTYPE_TTL_FAIL                         0xe
#define EPEDISCARDTYPE_TUNNEL_MTU_CHK_DIS               0x10
#define EPEDISCARDTYPE_INTERF_MTU_CHK_DIS               0x11
#define EPEDISCARDTYPE_LOGIC_PORT_CHK_DIS               0x12
#define EPEDISCARDTYPE_PORT_REFLECTIVE_CHK_DIS          0x1b
#define EPEDISCARDTYPE_NAT_PT_ICMP_ERR                  0x1e
#define EPEDISCARDTYPE_DS_NEXTHOP_DATA_VIOLATE          0x27
#define EPEDISCARDTYPE_ARP_MISS_DISCARD                 0x33
#define EPEDISCARDTYPE_INT_SINK_DIS                     0x39
#define EPEDISCARDTYPE_EVPN_HORIZON_SPLIT_DIS           0x3a  /*TMM*/
#define EPEDISCARDTYPE_SPAN_ONDROP_RSV_QUID             0x3b  /*TMM*/
#define IPEDISCARDTYPE_MPLS_ENTROPY_LABEL_CHK             0x3c
#define EPEDISCARDTYPE_NSH_SI_FAIL                      0x3d    /*AT*/

/*XPIPE */
#define SYS_USW_XPIPE_CLASSIFY_FILED_MAX                9

struct sys_usw_register_tcat_prof_s
{
    uint8  shift;
    uint8  length;

    uint8  profile_id;
    uint8  rsv;
};
typedef struct sys_usw_register_tcat_prof_s sys_usw_register_tcat_prof_t;

struct sys_usw_register_eco_tbl_s
{
    uint32  tbl_id;  /*table id*/
    uint32  fld_id;  /*file id*/
    uint16  num;     /*max table index*/
    uint32  value;   /*enable eco value*/
};
typedef struct sys_usw_register_eco_tbl_s sys_usw_register_eco_tbl_t;

sys_register_master_t* p_usw_register_master[CTC_MAX_LOCAL_CHIP_NUM_PP] = {NULL};

#define SYS_USW_HMAC_SET_IP_HEADER_HW(data, len)    { \
    uint32 _loop_ = 0, _temp_ = 0; \
    for (_loop_=0; _loop_<((len)>>1); _loop_++) {\
        _temp_ = data[_loop_]; \
        data[_loop_] = data[(len) - 1 - _loop_]; \
        data[(len) - 1 - _loop_] = _temp_; \
    }\
}

#define SYS_REGISTER_DBG_OUT(level, FMT, ...) \
    CTC_DEBUG_OUT(register, register, REGISTER_SYS, level, FMT, ## __VA_ARGS__)

#define SYS_USW_REGISTER_LOCK(lchip) \
    if (p_usw_register_master[lchip]->register_mutex) sal_mutex_lock(p_usw_register_master[lchip]->register_mutex)

#define SYS_USW_REGISTER_UNLOCK(lchip) \
    if (p_usw_register_master[lchip]->register_mutex) sal_mutex_unlock(p_usw_register_master[lchip]->register_mutex)

#define SYS_REGISTER_INIT_CHECK         \
    {                                \
        LCHIP_CHECK(lchip);          \
        if (!p_usw_register_master[lchip]) {           \
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_INFO, " Feature not initialized \n"); \
			return CTC_E_NOT_INIT; \
 } \
    }

#define SYS_IPV6_ADDRESS_SORT(val)           \
    {                                          \
        uint32 t;                          \
        t = val[0];               \
        val[0] = val[3]; \
        val[3] = t;               \
                                       \
        t = val[1];               \
        val[1] = val[2]; \
        val[2] = t;               \
    }

#define SYS_FEATURE_PP_LOOP_START(lchip, fea, pp_id) \
{\
    uint8 _pp_num_ = MCHIP_FEATURE_PP_EN(lchip, fea)? drv_vchip_get_pp_num(lchip) : 1;\
    pp_id = 0;\
    do{

#define SYS_FEATURE_PP_LOOP_END(pp_id) \
    }while(++pp_id < _pp_num_);\
}
#define SYS_PTP_MASK_DISABLE_MAC(bmp) \
if (index >= SYS_PTP_TS_RC_MAC && index < SYS_PTP_TS_RC_OAM && !((1 << ((index - SYS_PTP_TS_RC_MAC) >> 2))&bmp)) \
{ \
    continue; \
}

#define SYS_PTP_MASK_DISABLE_OAM(lchip) \
if (index >= SYS_PTP_TS_RC_OAM && index < SYS_PTP_TS_RC_METER && !((MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_OAM)))&& !((MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_NPM)))) \
{ \
    continue; \
}


extern sys_chip_master_t* p_usw_chip_master[CTC_MAX_LOCAL_CHIP_NUM_PP];
/****************************************************************************
 *
 * Function
 *
 *****************************************************************************/
 extern int32
sys_usw_datapath_wb_sync(uint8 lchip,uint32 app_id);

extern int32
sys_usw_flexe_wb_sync(uint8 lchip, uint32 app_id);

extern int32
sys_usw_ftm_wb_sync(uint8 lchip,uint32 app_id);

extern int32
sys_usw_acl_set_global_cfg(uint8 lchip, uint8 property, uint32 value);

extern uint8
sys_usw_acl_get_league_block(uint8 lchip, uint8 block_id, uint8 * block_list);

extern uint32
ctc_wb_get_sync_bmp(uint8 lchip, uint8 mod_id);
extern int32
sys_usw_flow_stats_32k_ram_init(uint8 lchip);
extern int32
sys_usw_mac_limit_set_mode(uint8 lchip, uint8 mode);
extern int32
sys_usw_mac_limit_get_mode(uint8 lchip, uint8* p_mode);
extern char*
ctcs_get_chip_name(uint8 lchip);
extern char*
ctc_get_chip_name();
#if defined E_UNIT && (FEATURE_MODE == 0)
extern int32
sys_usw_eunit_hw_reset(uint8 lchip, void* p_data);
extern int32
sys_usw_eunit_init(uint8 lchip);
extern int32
sys_usw_eunit_deinit(uint8 lchip);
extern int32
sys_usw_eunit_show_status(uint8 lchip, uint8 eunit_id, uint8 level);
#endif
extern int32
sys_usw_queue_drop_ecn_init(uint8 lchip, uint32 mode);

 STATIC int32
 _sys_usw_map_truncation_len_user_to_hw(uint16 len, uint8* len_hw, uint8* shift_hw)
 {
     *shift_hw = (len >> 8) & 0x7;
     if (CTC_IS_BIT_SET(*shift_hw, 2))
     {
         *shift_hw = 3;
     }
     else if (CTC_IS_BIT_SET(*shift_hw, 1))
     {
         *shift_hw = 2;
     }
     else if (CTC_IS_BIT_SET(*shift_hw, 0))
     {
         *shift_hw = 1;
     }
     else
     {
         *shift_hw = 0;
     }
     *len_hw = len / (1 << *shift_hw);

     if(len != (*len_hw << *shift_hw))
     {
        return CTC_E_INVALID_PARAM;
     }
     return CTC_E_NONE;
 }

 STATIC int32
 _sys_usw_discard_type_init(uint8 lchip)
 {

     uint32 cmd = 0;
     uint32 field_val = 0;
     ds_t   ds;


     /*NOT USED*/
     field_val = IPEDISCARDTYPE_RESERVED0;
     cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_pbbCheckFailDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_pbbOamDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_pbbCheckDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_pbbDecapDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeMplsCtl_t, IpeMplsCtl_tmplsOamDiscardType_f); /*TMPLS OAM (14 label)*/
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeMplsCtl_t, IpeMplsCtl_illegalWithElPktDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     /*MAC SECURITY (DOT1AE)*/
     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_DOT1AE_CHK);
     cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_unencryptedPktReceivedDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_dot1AeUnknownSciDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_dot1AeUnknownPktDiscard_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     /**< [TM] DOT1AE discard type */
     cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_dot1AePktRxOnDisabledPort_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     /**< [TM] OAM discard type  */
     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_OAM_FILTER_DIS);
     cmd = DRV_IOW(IpeLookupCtl_t, IpeLookupCtl_sBfdReflectorSrcPortCheckDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     /*ETH OAM CHK (LinkOam/ServiceOam vlan check)*/
     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_OAM_ETH_VLAN_CHK);
     cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_ethLinkOamDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_ethServOamDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     /*BFD TLL check */
     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_OAM_BFD_TTL_CHK);
     cmd = DRV_IOW(IpeLookupCtl_t, IpeLookupCtl_mplsBfdTtlCheckDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeOamCtl_t, IpeOamCtl_ipBfdTtlCheckDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_OAM_FILTER_DIS);
     cmd = DRV_IOW(IpeOamCtl_t, IpeOamCtl_oamFilterDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_OAM_NOT_FOUND);
     cmd = DRV_IOW(IpeOamCtl_t, IpeOamCtl_oamNotFindDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeOamCtl_t, IpeOamCtl_noMepMipDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_OAM_DISABLE);
     cmd = DRV_IOW(IpeMplsCtl_t, IpeMplsCtl_oamDisableDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     field_val = IPEDISCARDTYPE_MPLS_ES_LABEL_CHK;
     cmd = DRV_IOW(IpeMplsCtl_t, IpeMplsCtl_mplsEvpnEsiFailDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     field_val = EPEDISCARDTYPE_EVPN_HORIZON_SPLIT_DIS;
     cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_mplsEvpnHorizonSplitDiscard_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     field_val = EPEDISCARDTYPE_SPAN_ONDROP_RSV_QUID;
     if(DRV_FROM_AT(lchip))
     {
         cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_exceptionDiscardType_f);/*uc*/
         CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
         cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_spanOnDropDiscardType_f);/*mc*/
         CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     }
     else
     {
         cmd = DRV_IOW(EpeHdrAdjSpanCtl_t, EpeHdrAdjSpanCtl_spanOnDropDiscardType_f);
         CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     }
     /*TRILL check*/
     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_TRILL_CHK);
     cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_trillFilterDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeLookupCtl_t, IpeLookupCtl_trillInnverVlanCheckDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_trillOamDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_trillRpfCheckDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_trillVersionBfdCheckDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTrillCtl_t, IpeTrillCtl_trillVersionErrorDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_trillEsadiLoopbackDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTrillCtl_t, IpeTrillCtl_mcastAddressCheckDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_trillNonPortMacDiscard_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));


     /*WLAN check*/
     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_WLAN_CHK);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_capwapCipherStatusMisDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_capwapDtlsControlPacketDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_capwapKeepAlivePacketDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_dot11MgrCtlPktDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelIdCtl_t, IpeTunnelIdCtl_capwapCanNotReassembleDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_capwapPacketErrorDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelIdCtl_t, IpeTunnelIdCtl_capwapTunnelErrorDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_capwapStaStatusErrorDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_unknownDot11PacketDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_unknownCapwapPacketDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     /**< [TM] START */
     cmd = DRV_IOW(IpeAclQosCtl_t, IpeAclQosCtl_unknownCapwapPacketDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     /**< [TM] END */
     cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_capwapRoamingFwdErrorDiscard_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeTunnelIdCtl_t, IpeTunnelIdCtl_capwapFragPacketDiscard_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = IPEDISCARDTYPE_MACSEC_UNCONTROLLED_PORT_DIS;
     cmd = DRV_IOW(IpeHeaderAdjustCtl_t, IpeHeaderAdjustCtl_secTagDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_TUNNEL_ECN_DIS);
     cmd = DRV_IOW(IpeLookupCtl_t, IpeLookupCtl_tunnelEcnMisDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_EFM_DIS);
     cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_efmDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_ILOOP_DIS);
     cmd = DRV_IOW(IpeLoopbackHeaderAdjustCtl_t, IpeLoopbackHeaderAdjustCtl_bufRetrvDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_MPLS_ENTROPY_LABEL_CHK);
     cmd = DRV_IOW(IpeMplsCtl_t, IpeMplsCtl_entropyIsReservedLabelDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_MPLS_TP_MCC_SCC_DIS);
     cmd = DRV_IOW(IpeMplsCtl_t, IpeMplsCtl_mplstpMccSccDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_MPLS_MC_PKT_ERROR);
     cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_mplsMcPacketErrorDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_L2_EXCPTION_DIS);
     cmd = DRV_IOW(IpeRouteCtl_t, IpeRouteCtl_l2ExceptionDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_NAT_PT_CHK);
     cmd = DRV_IOW(IpeRouteCtl_t, IpeRouteCtl_ptErrorDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_DS_ACL_DIS);
     cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_aclDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_DS_PLC_DIS);
     cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_plcDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_SD_CHECK_DIS);
     cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_sdChkDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_CFLAX_SRC_ISOLATE_DIS);
     cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_cFlexSrcIsolateDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_EPEDISCARDTYPE_DS_ACL_DIS);
     cmd = DRV_IOW(EpeClassficationCtl_t, EpeClassficationCtl_aclDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = MCHIP_CAP(SYS_CAP_EPEDISCARDTYPE_DS_PLC_DIS);
     cmd = DRV_IOW(EpeClassficationCtl_t, EpeClassficationCtl_plcDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     field_val = IPEDISCARDTYPE_LOOPBACK_DIS;
     cmd = DRV_IOW(IpeLoopbackHeaderAdjustCtl_t, IpeLoopbackHeaderAdjustCtl_loopbackDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     /*INT check*/
     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_INT_CHK);
     cmd = DRV_IOW(IpeFwdIntCtl_t, IpeFwdIntCtl_discardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     /*UserId check*/
     sal_memset(ds, 0, sizeof(ds_t));
     cmd = DRV_IOR(IpeUserIdCtl_t, DRV_ENTRY_FLAG);
     CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
     field_val = 1;
     SetIpeUserIdCtl(V, hmacAbsentDiscard_f, ds, field_val);
     SetIpeUserIdCtl(V, hmacFailDiscard_f, ds, field_val);
     field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_USERID_CHK);
     SetIpeUserIdCtl(V, aluDiscardType_f, ds, field_val);
     SetIpeUserIdCtl(V, hmacFailDiscardType_f, ds, field_val);
     SetIpeUserIdCtl(V, hmacAbsentDiscardType_f, ds, field_val);
     SetIpeUserIdCtl(V, offsetViolationDiscardType_f, ds, field_val);
     SetIpeUserIdCtl(V, ttlCheckFailDiscardType_f, ds, field_val);
     SetIpeUserIdCtl(V, vMacMismatchDiscardType_f, ds, field_val);
     cmd = DRV_IOW(IpeUserIdCtl_t, DRV_ENTRY_FLAG);
     CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
     cmd = DRV_IOW(IpeUserIdSrCtl_t, IpeUserIdSrCtl_srCheckFailDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
     cmd = DRV_IOW(IpeUserIdSrCtl_t, IpeUserIdSrCtl_srSlLimitDiscardType_f);
     CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    /*Epe*/
    sal_memset(ds, 0, sizeof(ds_t));
    cmd = DRV_IOR(EpePktProcDiscardCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    field_val = EPEDISCARDTYPE_ARP_MISS_DISCARD;
    SetEpePktProcDiscardCtl(V, discardTypeArpMiss_f, ds, field_val);
    field_val = EPEDISCARDTYPE_INTERF_MTU_CHK_DIS;
    SetEpePktProcDiscardCtl(V, discardTypeInterfaceMtu_f, ds, field_val);
    field_val = EPEDISCARDTYPE_TUNNEL_MTU_CHK_DIS;
    SetEpePktProcDiscardCtl(V, discardTypeTunnelMtu_f, ds, field_val);
    field_val = EPEDISCARDTYPE_TTL_FAIL;
    SetEpePktProcDiscardCtl(V, discardTypeIpmcTtlFail_f, ds, field_val);
    SetEpePktProcDiscardCtl(V, discardTypeMplsLsp_f, ds, field_val);
    SetEpePktProcDiscardCtl(V, discardTypeMplsPath_f, ds, field_val);
    SetEpePktProcDiscardCtl(V, discardTypeMplsPw_f, ds, field_val);
    SetEpePktProcDiscardCtl(V, discardTypeMplsSpme_f, ds, field_val);
    SetEpePktProcDiscardCtl(V, discardTypeMplsSr_f, ds, field_val);
    SetEpePktProcDiscardCtl(V, discardTypeMplsTtlFail_f, ds, field_val);
    SetEpePktProcDiscardCtl(V, discardTypeRouteTtlFail_f, ds, field_val);
    SetEpePktProcDiscardCtl(V, discardTypeRwIpTtl_f, ds, field_val);
    SetEpePktProcDiscardCtl(V, discardTypeTrillTtlFail_f, ds, field_val);
    SetEpePktProcDiscardCtl(V, discardTypeTunnelTtl0_f, ds, field_val);
    field_val = EPEDISCARDTYPE_LOGIC_PORT_CHK_DIS;
    SetEpePktProcDiscardCtl(V, discardTypeLogicPortChk_f, ds, field_val);
    field_val = EPEDISCARDTYPE_NAT_PT_ICMP_ERR;
    SetEpePktProcDiscardCtl(V, discardTypeNatPtIcmpErr_f, ds, field_val);
    field_val = EPEDISCARDTYPE_PORT_REFLECTIVE_CHK_DIS;
    SetEpePktProcDiscardCtl(V, discardTypePortReflectiveChk_f, ds, field_val);
    cmd = DRV_IOW(EpePktProcDiscardCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    field_val = EPEDISCARDTYPE_INT_SINK_DIS;
    cmd = DRV_IOW(DsIntEditCtl_t, DsIntEditCtl_intSinkOpFailDiscardType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    field_val = MCHIP_CAP(SYS_CAP_IPEDISCARD_INT_CHK); /*TODO temply use INT_CHK*/
    cmd = DRV_IOW(IpePreLookupCtl_t, IpePreLookupCtl_nshCheckFailDiscardType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    field_val = EPEDISCARDTYPE_TTL_FAIL;
    cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_nshBhTtlCheckFailDiscardType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    field_val = EPEDISCARDTYPE_NSH_SI_FAIL;
    cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_nshSpiSiCheckFailDiscardType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    field_val = EPEDISCARDTYPE_DS_NEXTHOP_DATA_VIOLATE;
    cmd = DRV_IOW(NextHopPointerXlateCtl_t, NextHopPointerXlateCtl_dropNhpPtrOverflowType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

     return CTC_E_NONE;
 }



/* mode 0: txThrd0=3, txThrd1=4; mode 1: txThrd0=5, txThrd1=11; if cut through enable, default use mode 1 */
int32 sys_usw_net_tx_threshold_cfg(uint8 lchip, uint16 mode)
{
#if 0
    uint32 cmd = 0;
    NetTxTxThrdCfg0_m net_tx_cfg;

    if(1 == mode)
    {
        cmd = DRV_IOR(NetTxTxThrdCfg0_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &net_tx_cfg));
        SetNetTxTxThrdCfg0(V, txThrd0_f, &net_tx_cfg, 5);
        SetNetTxTxThrdCfg0(V, txThrd1_f, &net_tx_cfg, 11);
        cmd = DRV_IOW(NetTxTxThrdCfg0_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &net_tx_cfg));

        cmd = DRV_IOR(NetTxTxThrdCfg1_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &net_tx_cfg));
        SetNetTxTxThrdCfg0(V, txThrd0_f, &net_tx_cfg, 5);
        SetNetTxTxThrdCfg0(V, txThrd1_f, &net_tx_cfg, 11);
        cmd = DRV_IOW(NetTxTxThrdCfg1_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &net_tx_cfg));
    }
    else
    {
        cmd = DRV_IOR(NetTxTxThrdCfg0_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &net_tx_cfg));
        SetNetTxTxThrdCfg0(V, txThrd0_f, &net_tx_cfg, 3);
        SetNetTxTxThrdCfg0(V, txThrd1_f, &net_tx_cfg, 4);
        cmd = DRV_IOW(NetTxTxThrdCfg0_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &net_tx_cfg));

        cmd = DRV_IOR(NetTxTxThrdCfg1_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &net_tx_cfg));
        SetNetTxTxThrdCfg0(V, txThrd0_f, &net_tx_cfg, 3);
        SetNetTxTxThrdCfg0(V, txThrd1_f, &net_tx_cfg, 4);
        cmd = DRV_IOW(NetTxTxThrdCfg1_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &net_tx_cfg));
    }
#endif
    return CTC_E_NONE;
}
#if (FEATURE_MODE == 0)
STATIC int32
_sys_usw_tcam_bist_check(uint8 lchip)
{
    uint8 loop;
    uint8 loop1;
    uint8 loop1_max;
    uint8 error_mem_id[32] = {0};
    uint8 error_cnt = 0;
    uint16 error_entry_cnt;
    sys_diag_tcam_bmp invalid_bmp;
    uint8 tmp_error_mem_id;

    /*0. diag init*/
    CTC_ERROR_RETURN(sys_usw_diag_init(lchip, NULL));

    /*1. do mbist*/
    CTC_ERROR_RETURN(sys_usw_diag_tcam_mbist_api(lchip, error_mem_id, &error_cnt));
    if(0 == error_cnt)
    {
        sys_usw_diag_deinit(lchip);
        return CTC_E_NONE;
    }

    /*do functioin bist to find the error entry*/
    for(loop=0; loop < error_cnt; loop++)
    {
        loop1_max = (DRV_FTM_LPM_TCAM_KEY0 <= error_mem_id[loop] && error_mem_id[loop] < (DRV_FTM_LPM_TCAM_KEY0 + DRV_CONST(DRV_MAX_LPM_TCAM_NUM))) ? 4:1;

        for(loop1=0; loop1 < loop1_max; loop1++)
        {
            sal_memset(&invalid_bmp, 0, sizeof(invalid_bmp));
            error_entry_cnt = 0;
            tmp_error_mem_id = error_mem_id[loop]+loop1;
            CTC_ERROR_RETURN(sys_usw_diag_tcam_function_bist_api(lchip, tmp_error_mem_id, &error_entry_cnt, &invalid_bmp));
            drv_mem_map(lchip, tmp_error_mem_id, invalid_bmp);
            if(DRV_FTM_LPM_TCAM_KEY0 <= tmp_error_mem_id && tmp_error_mem_id <(DRV_FTM_LPM_TCAM_KEY0 + DRV_CONST(DRV_MAX_LPM_TCAM_NUM)))
            {
                drv_lpm_tcam_map(lchip, tmp_error_mem_id, invalid_bmp);
            }
        }
    }
    drv_usw_ftm_alloc_tcam(lchip, DRV_FTM_TCAM_TYPE_IGS_ACL0, DRV_FTM_TCAM_TYPE_STATIC_TCAM, 1);
    drv_usw_lpm_tcam_init_blknum(lchip);
    sys_usw_diag_deinit(lchip);
    return CTC_E_NONE;
}
#endif
STATIC int32
_sys_usw_lkp_ctl_init(uint8 lchip)
{
    CTC_ERROR_RETURN(sys_usw_ftm_lkp_register_init(lchip));
    return CTC_E_NONE;
}

int32
sys_usw_lkup_ttl_index(uint8 lchip, uint8 ttl, uint32* ttl_index)
{
    uint32 cmd;
    uint8 index = 0;
    uint32 mpls_ttl = 0;
    uint8 bfind = 0;
    SYS_REGISTER_INIT_CHECK;

    for (index = 0; index < 16; index++)
    {
        if (DRV_IS_DUET2(lchip) || DRV_IS_TSINGMA(lchip))
        {
            cmd = DRV_IOR(EpeL3EditMplsTtl_t, EpeL3EditMplsTtl_array_0_ttl_f +  index);
        }
        else
        {
            cmd = DRV_IOR(EpeL3EditMplsCtl_t, EpeL3EditMplsCtl_g_0_ttl_f +  index);
        }

        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &mpls_ttl));

        if (mpls_ttl >= ttl)
        {
            *ttl_index = index;
            bfind = 1;
            break;
        }
    }

    if (bfind)
    {
        return CTC_E_NONE;
    }

    return CTC_E_INVALID_PARAM;
}

int32
sys_usw_lkup_ttl_value(uint8 lchip, uint8 ttl_index, uint8* ttl)
{
    uint32 cmd;

    uint32 mpls_ttl = 0;
    SYS_REGISTER_INIT_CHECK;
    CTC_MAX_VALUE_CHECK(ttl_index, 15);

    if (DRV_IS_DUET2(lchip) || DRV_IS_TSINGMA(lchip))
    {
        cmd = DRV_IOR(EpeL3EditMplsTtl_t, EpeL3EditMplsTtl_array_0_ttl_f +  ttl_index);
    }
    else
    {
        cmd = DRV_IOR(EpeL3EditMplsCtl_t, EpeL3EditMplsCtl_g_0_ttl_f +  ttl_index);
    }

    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &mpls_ttl));
    *ttl = mpls_ttl;

    return CTC_E_NONE;
}

int32
_sys_usw_misc_ctl_init(uint8 lchip)
{
    uint32 cmd = 0;
    ds1_t ds;
    uint32 max_index = 0;
    uint8 lgchip = 0;
    uint32 field_val = 0;
    uint32 val = 0;
    uint16 i = 0;
    uint32 truncate_en[5] = {0};
    uint32 discard_cancel_edit[2]={0};
    NetTxTruncateEnableCtl_m net_tx_truncate_en_ctl;
    IpeFwdCtl_m ipe_fwd_ctl;
    IpeAclQosCtl_m ipe_acl_qos_ctl;
    hw_mac_addr_t mac_da;
    uint8 step = SclEngineCtl_g0_1_isSclType_f - SclEngineCtl_g0_0_isSclType_f ;
    uint8 tunnel_step = UserIdHashLookupTypeMapCtl_gArray_1_isTunnelIdHash_f - UserIdHashLookupTypeMapCtl_gArray_0_isTunnelIdHash_f ;
    uint8 step1 = PortIsolationForwardTypeMapCtl_gFwdType_1_typeValue_f - PortIsolationForwardTypeMapCtl_gFwdType_0_typeValue_f;
    int32 ret = CTC_E_NONE;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
#ifdef AT_TODO
    uint32 source_chip_discard[4] = {0};
#endif

    sys_usw_get_gchip_id(lchip, &lgchip);

    /*init cfgTsUseIntRefClk */
    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(SupDskCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    field_val = 1;
    SetSupDskCfg(V, cfgTsUseIntRefClk_f, &ds, field_val);
    cmd = DRV_IOW(SupDskCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(NetTxMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    field_val = 1;
    SetNetTxMiscCtl(V, netTxResPauseEn_f, &ds, field_val);      /* AT for fast PFC */
    field_val = 0x11;
    SetNetTxMiscCtl(V, cfgMinPktLen0_f, &ds, field_val);
    cmd = DRV_IOW(NetTxMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    if (!DRV_FROM_AT(lchip))
    {
    cmd = DRV_IOW(EpeScheduleMiscCtl_t, EpeScheduleMiscCtl_toMiscMinPktLen_f);
    SYS_SET_FIELD_TBL_ALL_DP(lchip, cmd, field_val);

    cmd = DRV_IOW(EpeScheduleMiscCtl_t, EpeScheduleMiscCtl_toNetMinPktLen_f);
    SYS_SET_FIELD_TBL_ALL_DP(lchip, cmd, field_val);
    }
    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(IpeHeaderAdjustCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeHeaderAdjustCtl(V, packetHeaderBypassAll_f, ds, 0);
    SetIpeHeaderAdjustCtl(V, gemPortBitType_f, ds, 1);
    SetIpeHeaderAdjustCtl(V, maxLocalPhyPort_f, ds, MCHIP_CAP(SYS_CAP_PER_SLICE_PORT_NUM) -1);
    SetIpeHeaderAdjustCtl(V, sniffingPktUsePortMode_f, ds, 1);
    cmd = DRV_IOW(IpeHeaderAdjustCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(&ds, 0, sizeof(ds));
    cmd = DRV_IOR(SclEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetSclEngineCtl(V, ipdaIndexMismatchHashType0Mode_f, ds, 1);
    SetSclEngineCtl(V, ipdaIndexMismatchHashType1Mode_f, ds, 1);
    for (i = 0;i <=DRV_ENUM(DRV_USERIDPORTHASHTYPE_SCLTYPE_END);i++ )
    {
        SetSclEngineCtl(V, g0_0_isSclType_f + i*step, ds, 1);
        SetSclEngineCtl(V, g1_0_isSclType_f + i*step, ds, 1);
    }
    SetSclEngineCtl(V, nshExtType_f, ds, SYS_PARSER_EXT_TYPE_NSH);
    cmd = DRV_IOW(SclEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(&ds, 0, sizeof(ds));
    cmd = DRV_IOR(UserIdHashLookupTypeMapCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    for (i = DRV_ENUM(DRV_USERIDHASHTYPE_TUNNELTYPE_START); i <=DRV_ENUM(DRV_USERIDHASHTYPE_TUNNELTYPE_END);i++ )
    {
        SetUserIdHashLookupTypeMapCtl(V, gArray_0_isTunnelIdHash_f + i*tunnel_step, ds, 1);
        SetUserIdHashLookupTypeMapCtl(V, gArray_0_defaultEntryOffset_f + i*tunnel_step, ds,( i-DRV_ENUM(DRV_USERIDHASHTYPE_TUNNELTYPE_START)));
    }
    cmd = DRV_IOW(UserIdHashLookupTypeMapCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(IpeUserIdCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeUserIdCtl(V, parserLengthErrorMode_f, ds, 0);
    SetIpeUserIdCtl(V, layer2ProtocolTunnelLmDisable_f, ds, 1);
    SetIpeUserIdCtl(V, useBypassIngressEdit_f, ds, 1);
    /**< [TM] Hash match default entry while not match ip da */
    SetIpeUserIdCtl(V, ipdaIndexMismatchHashType0Mode_f, ds, 1);
    SetIpeUserIdCtl(V, ipdaIndexMismatchHashType1Mode_f, ds, 1);
    /*SetIpeUserIdCtl(V, tcamLookup2NotImpactPopDefaultEntry_f, ds, 1);
    SetIpeUserIdCtl(V, tcamLookup3ForRouterMac_f, ds, 1);*/

    /**< [TM] Skip IP Binding Check for L3 ARP Packet */
    SetIpeUserIdCtl(V, arpPktSkipIpBindingCheck_f, ds, 0);
    /**< [TM] Wlan Module: Whether do hash lookup for capwap packet */
    SetIpeUserIdCtl(V, splitMacTunnel1LookupEn_f, ds, 1);
    /**< [TM] "0x01"=UserId{2,0,1,3}        "0x02"=UserId{2,3,0,1}
                   "0x03"=UserId{0,2,1,3}        "0x04"=UserId{2,0,3,1}
                   "0x00"=UserId{0,1,2,3}        keep compatible with D2       */
    SetIpeUserIdCtl(V, userIdResultPriorityMode_f, ds, 0x00);

    /*
    randomLogShift is 5, so random log percent 0~100 % and step is 0.0031%
    */
    SetIpeUserIdCtl(V, randomLogShift_f, ds, MCHIP_CAP(SYS_CAP_RANDOM_LOG_SHIFT));

    SetIpeUserIdCtl(V, hmacAbsentCheckEn_f, ds, 1);     /*TMM...*/
    SetIpeUserIdCtl(V, hmacAbsentException_f, ds, 1);   /*TMM...*/
    SetIpeUserIdCtl(V, hmacAbsentExceptionSubindex_f, ds, 56);  /*TMM...SYS_NORMAL_EXCP_SUB_TYPE_HMAC_CHECK*/
    SetIpeUserIdCtl(V, offsetViolationMode_f, ds, 1);  /*TMM...If payload offset invalid, discard*/
    SetIpeUserIdCtl(V, onuPassIgnore_f, ds, 0);     /*TMM...onu pass throuth default support by sdk*/
    SetIpeUserIdCtl(V, ttlLimit_f, ds, 1);  /*TMM...*/
    SetIpeUserIdCtl(V, vrfIdLoopEn_f, ds, 1);
    cmd = DRV_IOW(IpeUserIdCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    cmd = DRV_IOR(IpeUserIdXCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeUserIdXCtl(V, disableXPI_f, ds, 1);
    cmd = DRV_IOW(IpeUserIdXCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

	sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(IpeSclFlowCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeSclFlowCtl(V, followGreProtocol_f, ds, 1);
    cmd = DRV_IOW(IpeSclFlowCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));


    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(IpeIntfMapperCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeIntfMapperCtl(V, allowMcastMacSa_f,                ds, 0);
    SetIpeIntfMapperCtl(V, bypassAllDisableLearning_f,       ds, 1);
    SetIpeIntfMapperCtl(V, bypassPortCrossConnectDisable_f,  ds, 1);
    SetIpeIntfMapperCtl(V, dhcpBroadcastRoutedPortDiscard_f, ds, 0);
    SetIpeIntfMapperCtl(V, dhcpExceptionSubIndex_f,          ds, CTC_L3PDU_ACTION_INDEX_DHCP);
    SetIpeIntfMapperCtl(V, dhcpUnicastDiscard_f,             ds, 0);
    SetIpeIntfMapperCtl(V, dhcpUnicastExceptionDisable_f,    ds, 1);
    SetIpeIntfMapperCtl(V, discardSameIpAddr_f,              ds, 0);
    SetIpeIntfMapperCtl(V, discardSameMacAddr_f,             ds, 1);
    SetIpeIntfMapperCtl(V, fipExceptionSubIndex_f,          ds, CTC_L2PDU_ACTION_INDEX_FIP);
    SetIpeIntfMapperCtl(V, addDefaultSvlanUpdateTpid_f,          ds, 1);
    SetIpeIntfMapperCtl(V, learningDisableMode_f,          ds, 1);
    SetIpeIntfMapperCtl(V, arpCtlMode_f,                     ds, 1);    /*TMM. arp exception by userid*/
    SetIpeIntfMapperCtl(V, igmpSnoopEnMode_f,                ds, 1);    /*TMM*/
    SetIpeIntfMapperCtl(V, vxlanAcRouterMacUseInner_f,       ds, 1);    /*AT*/
    cmd = DRV_IOW(IpeIntfMapperCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(IpeMplsCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeMplsCtl(V, minInterfaceLabel_f, ds, 0);
    SetIpeMplsCtl(V, oamAlertLabel0_f, ds, 14);
    SetIpeMplsCtl(V, oamAlertLabel1_f, ds, 13);
    SetIpeMplsCtl(V, mplsOffsetBytesShift_f, ds, 2);
    SetIpeMplsCtl(V, useFirstLabelTtl_f, ds, 0);
    SetIpeMplsCtl(V, galSbitCheckEn_f, ds, 1);
    SetIpeMplsCtl(V, galTtlCheckEn_f, ds, 1);
    SetIpeMplsCtl(V, entropyLabelTtlCheckEn_f, ds, 1);
    SetIpeMplsCtl(V, mplsUseBypassIngressEdit_f, ds, 1);
    SetIpeMplsCtl(V, allAchAsOamEn_f, ds, 0);
    SetIpeMplsCtl(V, aclQosUseOuterInfoMode_f, ds, 0);
    SetIpeMplsCtl(V, metaDataEnForAll_f, ds, 0);
    SetIpeMplsCtl(V, trustMplsTcForce_f, ds, 0);
    SetIpeMplsCtl(V, mplsVrfIdLoopEn_f, ds, 1);
    cmd = DRV_IOW(IpeMplsCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(IpeAclMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeAclMiscCtl(V, seqCheckEn_f, ds, 1);
    cmd = DRV_IOW(IpeAclMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(EpePktRewriteMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetEpePktRewriteMiscCtl(V, seqCheckEn_f, ds, 1);
    cmd = DRV_IOW(EpePktRewriteMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(SvcPolicingMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetSvcPolicingMiscCtl(V, reqPtrMax_f, ds, 8191);
    cmd = DRV_IOW(SvcPolicingMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(IpeTunnelIdCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeTunnelIdCtl(V, routeObeyStp_f, ds, 1);
    SetIpeTunnelIdCtl(V, tunnelforceSecondParserEn_f, ds, 0x3ff);
    SetIpeTunnelIdCtl(V, innerParserMaxOffset_f, ds, 128);
    SetIpeTunnelIdCtl(V, geneveOptionPktDoDecapsAndForward_f, ds, 1);   /* enable geneve option pkt do decapes and forward*/
    cmd = DRV_IOW(IpeTunnelIdCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));


    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(IpeLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeLookupCtl(V, globalVrfIdLookupEn_f, ds, 1);
    SetIpeLookupCtl(V, pimSnoopingEn_f, ds, 1);
    SetIpeLookupCtl(V, stpBlockBridgeDisable_f, ds, 0);
    SetIpeLookupCtl(V, noIpMcastMacLookup_f, ds, 0);
    SetIpeLookupCtl(V, stpBlockLayer3_f, ds, 0);
    SetIpeLookupCtl(V, trillMbitCheckDisable_f, ds, 0);
    SetIpeLookupCtl(V, routedPortDisableBcastBridge_f, ds, 0);
    SetIpeLookupCtl(V, greFlexProtocol_f, ds, 0);
    SetIpeLookupCtl(V, greFlexPayloadPacketType_f, ds, 0);
    SetIpeLookupCtl(V, trillInnerVlanCheck_f, ds, 1);
    SetIpeLookupCtl(V, trillVersion_f, ds, 0);
    SetIpeLookupCtl(V, trillUseInnerVlan_f, ds, 1);
    SetIpeLookupCtl(V, metadataSendFid_f, ds, 1);
    SetIpeLookupCtl(V, upMepMacDaLkupMode_f, ds, 1);
    SetIpeLookupCtl(V, ecnAware_f, ds, 6); /*only TCP and UDP ECN Aware*/

    SetIpeLookupCtl(V, flowHashPrBusGlobalMode_f, ds, 1);
    SetIpeLookupCtl(V, hashFieldSrcLocalPortMode_f, ds, 1);
    SetIpeLookupCtl(V, macSaIsAllZeroDisableMacSaLookup_f, ds, 1);
    SetIpeLookupCtl(V, enableAclDecapSkipGreOption_f, ds, 1);   /*TMM.*/
    SetIpeLookupCtl(V, vxlanCategoryIdValid_f, ds, 1);   /*TMM.*/
    SetIpeLookupCtl(V, pimRegisterPktSnoopingDisable_f, ds, 1);   /*TMM.*/

    cmd = DRV_IOW(IpeLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    cmd = DRV_IOR(IpeFwdCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_ctl));
    SetIpeFwdCtl(V, ecnPriorityCritical_f, &ipe_fwd_ctl, 0);
    SetIpeFwdCtl(V, chipId_f, &ipe_fwd_ctl, lgchip);
    SetIpeFwdCtl(V, discardFatal_f, &ipe_fwd_ctl, 0);
    SetIpeFwdCtl(V, headerHashMode_f, &ipe_fwd_ctl, 0);
    SetIpeFwdCtl(V, linkOamColor_f, &ipe_fwd_ctl, 0);
    SetIpeFwdCtl(V, logOnDiscard_f, &ipe_fwd_ctl, 0x3FFFF);
    SetIpeFwdCtl(V, rxEtherOamCritical_f, &ipe_fwd_ctl, 0);
    SetIpeFwdCtl(V, portExtenderMcastEn_f, &ipe_fwd_ctl, 0);
    SetIpeFwdCtl(V, forceExceptLocalPhyPort_f, &ipe_fwd_ctl, 0);
    SetIpeFwdCtl(V, cutThroughCareChannelState_f, &ipe_fwd_ctl, 1);
    SetIpeFwdCtl(V, cutThroughDisableChannel_f, &ipe_fwd_ctl, 64);
    SetIpeFwdCtl(V, elephantFlowColor_f, &ipe_fwd_ctl, CTC_QOS_COLOR_GREEN);
    SetIpeFwdCtl(V, oamObeyAclDiscard_f, &ipe_fwd_ctl, 1);
    SetIpeFwdCtl(V, aclRedirectForceMacKnown_f, &ipe_fwd_ctl, 1);
    SetIpeFwdCtl(V, iloopBheaderSourePortMode_f, &ipe_fwd_ctl, 0);
    SetIpeFwdCtl(V, minIloopPortBheaderSourePort_f, &ipe_fwd_ctl, SYS_RSV_PORT_IP_TUNNEL);
    SetIpeFwdCtl(V, maxIloopPortBheaderSourePort_f, &ipe_fwd_ctl, SYS_RSV_PORT_IP_TUNNEL);
    SetIpeFwdCtl(V, cFlexAclDscapValidMode_f, &ipe_fwd_ctl, 0);   /*TMM*/
    SetIpeFwdCtl(V, secPortIsolationGroupIdClearEn_f, &ipe_fwd_ctl, 1);   /*AT*/
    SetIpeFwdCtl(V, secStatsPtrClearEn_f, &ipe_fwd_ctl, 1);   /*AT*/
    SetIpeFwdCtl(V, sectruncationClearEn_f, &ipe_fwd_ctl, 1);   /*AT*/
    cmd = DRV_IOW(IpeFwdCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_ctl));
    /**< [TM] START */
    cmd = DRV_IOR(IpeAclQosCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_acl_qos_ctl));
    SetIpeAclQosCtl(V, logOnDiscard_f, &ipe_acl_qos_ctl, 0x3FFFF);
    SetIpeAclQosCtl(V, discardFatal_f, &ipe_acl_qos_ctl, 0);
    SetIpeAclQosCtl(V, oamBypassPolicingOp_f, &ipe_acl_qos_ctl, 1);
    SetIpeAclQosCtl(V, oamBypassStormCtlOp_f, &ipe_acl_qos_ctl, 1);
    SetIpeAclQosCtl(V, fromCpuOrOamBypassPolicing_f, &ipe_acl_qos_ctl, 1);
    SetIpeAclQosCtl(V, fromCpuOrOamBypassStorm_f, &ipe_acl_qos_ctl, 1);
    SetIpeAclQosCtl(V, fatalExceptionForceMacKnown_f, &ipe_acl_qos_ctl, 1);
    SetIpeAclQosCtl(V, forceBackClearSrcCidValidEn_f, &ipe_acl_qos_ctl, 1);
    SetIpeAclQosCtl(V, vplsDecapsPktForwardingTypeMode_f, &ipe_acl_qos_ctl, 1);
    SetIpeAclQosCtl(V, aclRedirectClearPreFwdInfoOp_f, &ipe_acl_qos_ctl, 1);    /*TMM*/
    SetIpeAclQosCtl(V, aclRedirectClearPktFwdType_f, &ipe_acl_qos_ctl, 1);      /*TMM*/
    SetIpeAclQosCtl(V, reservedCategoryId_f, &ipe_acl_qos_ctl, CTC_ACL_DEFAULT_CID);    /*TMM*/
    SetIpeAclQosCtl(V, ptpOffsetAdj_f, &ipe_acl_qos_ctl, 1);    /*AT*/
    SetIpeAclQosCtl(V, tunnelEcmpNewMode_f, &ipe_acl_qos_ctl, 1);    /*AT*/
    cmd = DRV_IOW(IpeAclQosCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_acl_qos_ctl));

    field_val = 1;
    cmd = DRV_IOW(EpeClassficationCtl_t, EpeClassficationCtl_fromCpuOrOamBypassPolicing_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    cmd = DRV_IOW(IpeUserIdFlowCtl_t, IpeUserIdFlowCtl_seedSelectEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    /**< [TM] END */
    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(EpeHdrAdjustCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetEpeHdrAdjustCtl(V, mplsOfModeAutoDetectIp_f, ds, 1);
    SetEpeHdrAdjustCtl(V, portExtenderMcastEn_f, ds, 0);
    if (!DRV_IS_DUET2(lchip))
    {
        SetEpeHdrAdjustCtl(V, mplsSbfdEn_f, ds, 1);
    }

    SetEpeHdrAdjustCtl(V, mplsOfModeEn_f, ds, 1);
    SetEpeHdrAdjustCtl(V, egressPortMapEn_f, ds, 0x3);
    SetEpeHdrAdjustCtl(V, destChannelRemove_f, ds, (1<<4));/*TMM, iloop remove bytes*/
    SetEpeHdrAdjustCtl(V, vxlanCompatibilityMode_f, ds, 1);/*TMM*/
    SetEpeHdrAdjustCtl(V, bypassPopNhpIdToPointerTable_f, ds, 1);/*AT*/
    SetEpeHdrAdjustCtl(V, bypassEpeCfHdrLenAdjCtl_f, ds, 0x1);/*AT*/
    SetEpeHdrAdjustCtl(V, cflexParserEn_f, ds, 1);/*AT*/
    SetEpeHdrAdjustCtl(V, fabricToFarbicPktForceEpeParser_f, ds, 1);/*AT*/
    SetEpeHdrAdjustCtl(V, bypassEpeRecoverIsSpanPkt_f, ds, 1);
    SetEpeHdrAdjustCtl(V, oamAlwaysUseEgressEdit_f, ds, 1);/*AT*/
    SetEpeHdrAdjustCtl(V, oamPacketTypeSkipParser_f, ds, 1);/*AT*/
    cmd = DRV_IOW(EpeHdrAdjustCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(IpeTunnelDecapCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeTunnelDecapCtl(V, greFlexPayloadPacketType_f, ds, 0);
    SetIpeTunnelDecapCtl(V, greFlexProtocol_f, ds, 0x0800);
    SetIpeTunnelDecapCtl(V, greOption2CheckEn_f, ds, 1);
    SetIpeTunnelDecapCtl(V, ipTtlLimit_f, ds, 1);
    SetIpeTunnelDecapCtl(V, offsetByteShift_f, ds, (DRV_IS_DUET2(lchip)) ? 1 : 0);
    SetIpeTunnelDecapCtl(V, tunnelMartianAddressCheckEn_f, ds, 1);
    SetIpeTunnelDecapCtl(V, mcastAddressMatchCheckDisable_f, ds, 0);
    SetIpeTunnelDecapCtl(V, trillTtl_f, ds, 1);
    SetIpeTunnelDecapCtl(V, trillversionCheckEn_f, ds, 1);
    SetIpeTunnelDecapCtl(V, trillVersion_f, ds, 0);
    SetIpeTunnelDecapCtl(V, trillBfdCheckEn_f, ds, 1);
    SetIpeTunnelDecapCtl(V, trillBfdHopCount_f, ds, 0x30);
    SetIpeTunnelDecapCtl(V, ipOptionTunnelFatalException_f, ds, 1);
    SetIpeTunnelDecapCtl(V, greDecapSkipOptionValid_f, ds, 0xF);
    SetIpeTunnelDecapCtl(V, mplsSnoopMode_f, ds, 1);
    SetIpeTunnelDecapCtl(V, tunnelVrfIdLoopEn_f, ds, 1);
    cmd = DRV_IOW(IpeTunnelDecapCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));


    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(IpeLearningCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeLearningCtl(V, vsiSecurityExceptionEn_f, ds, 1);
    SetIpeLearningCtl(V, pendingEntrySecurityDisable_f, ds, 0);
    SetIpeLearningCtl(V, srcMismatchDiscardException_f, ds, 1);
    SetIpeLearningCtl(V, aclCareMacSecurityEn_f, ds, 0x1);      /*only enable black hole mac discard*/
    SetIpeLearningCtl(V, portSecurityType_f, ds, 1);
    SetIpeLearningCtl(V, stationMovePortAuthEn_f, ds, 1);       /* TMM mac auth */
    cmd = DRV_IOW(IpeLearningCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(IpeTrillCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeTrillCtl(V, versionCheckEn_f, ds, 1);
    SetIpeTrillCtl(V, trillBypassDenyRoute_f, ds, 0);
    cmd = DRV_IOW(IpeTrillCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(MetFifoCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetMetFifoCtl(V, chipId_f, ds, lgchip);
    SetMetFifoCtl(V, portCheckEn_f, ds, 1);
    SetMetFifoCtl(V, discardMetLoop_f, ds, 1);
    SetMetFifoCtl(V, portBitmapNextHopPtr_f, ds, 1);
    SetMetFifoCtl(V, portBitmapLagMode_f, ds, 0);
    SetMetFifoCtl(V, vxlanCompatibilityMode_f, ds, 1);
    SetMetFifoCtl(V, dsMetMemoryMax_f, ds, 0x1FFFF);
    SetMetFifoCtl(V, oamElogUseExcpDestMap_f, ds, 0);
    cmd = DRV_IOW(MetFifoCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(PreBufferRetrieveCtl_t, DRV_ENTRY_FLAG);
    SetPreBufferRetrieveCtl(V, vxlanCompatibilityMode_f, ds, 1);
    cmd = DRV_IOW(PreBufferRetrieveCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(EpeL2EtherType_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetEpeL2EtherType(V, array_0_etherType_f, ds, 0);
    SetEpeL2EtherType(V, array_1_etherType_f, ds, 0);
    cmd = DRV_IOW(EpeL2EtherType_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(EpeNextHopCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    /*Temple disable hyrid port*/
    SetEpeNextHopCtl(V, tagPortBitMapEn_f, ds, 1);
    SetEpeNextHopCtl(V, discardReflectiveBridge_f, ds, 1);
    SetEpeNextHopCtl(V, forceBridgeL3Match_f, ds, 1);
    SetEpeNextHopCtl(V, discardLogicTunnelMatch_f, ds, 1);
    SetEpeNextHopCtl(V, routeObeyIsolate_f, ds, 0);
    SetEpeNextHopCtl(V, mirrorObeyDiscard_f, ds, 0);
    SetEpeNextHopCtl(V, denyDuplicateMirror_f, ds, 1);
    SetEpeNextHopCtl(V, parserErrorIgnore_f, ds, 0);
    SetEpeNextHopCtl(V, discardSameIpAddr_f, ds, 0);
    SetEpeNextHopCtl(V, discardSameMacAddr_f, ds, 1);
    SetEpeNextHopCtl(V, cbpTciRes2CheckEn_f, ds, 0);
    SetEpeNextHopCtl(V, pbbBsiOamOnEgsCbpEn_f, ds, 0);
    SetEpeNextHopCtl(V, terminatePbbBvOamOnEgsPip_f, ds, 0);
    SetEpeNextHopCtl(V, pbbBvOamOnEgsPipEn_f, ds, 0);
    SetEpeNextHopCtl(V, routeObeyStp_f, ds, 1);
    SetEpeNextHopCtl(V, parserLengthErrorMode_f, ds, 3);
    SetEpeNextHopCtl(V, oamIgnorePayloadOperation_f, ds, 1);
    SetEpeNextHopCtl(V, etherOamUsePayloadOperation_f, ds, 1);
    SetEpeNextHopCtl(V, bridgeOpMapping_f, ds, 0x1C);
    SetEpeNextHopCtl(V, bypassDisableInsertCidTagBitmap_f, ds, 0x2);
    SetEpeNextHopCtl(V, oamSdChkEn_f, ds, 0x1);
    SetEpeNextHopCtl(V, replaceDscpObeyNhpOpType_f, ds, 0x1);
    /*
    randomLogShift is 5, so random log percent 0~100 % and step is 0.0031%
    */
    if (DRV_FROM_TMM(lchip))
    {
        SetEpeNextHopCtl(V, randomLogShift_f, ds, 7);
    }
    else
    {
        SetEpeNextHopCtl(V, randomLogShift_f, ds, 5);
    }
    SetEpeNextHopCtl(V, seedSelectEn_f, ds, 1);
    SetEpeNextHopCtl(V, useGlbDstPortDefaultVid_f, ds, 1);
    SetEpeNextHopCtl(V, flexEditPtrMode_f, ds, 1);/*inner l3edit*/
    SetEpeNextHopCtl(V, flexEditPtrType_f, ds, 1);

    SetEpeNextHopCtl(V, scl0DvpGidMask_f, ds, 0x3FF);/*decide SYS_LP_GRP_ID_MAX*/
    SetEpeNextHopCtl(V, scl1DvpGidMask_f, ds, 0x7C00);/*decidde SYS_ISOLATION_ID_MAX*/
    SetEpeNextHopCtl(V, scl0MetadataMask_f, ds, 0x7FFF);
    SetEpeNextHopCtl(V, scl1MetadataMask_f, ds, 0x7FFF);
    if((DRV_IS_TMM(lchip) && SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) || DRV_IS_TMG(lchip) || DRV_FROM_AT(lchip))
    {
        SetEpeNextHopCtl(V, editBypassValid_f, ds, 1);
    }
    cmd = DRV_IOW(EpeNextHopCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(EpeHeaderEditCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    val = DRV_FROM_AT(lchip)? 0x103F: 0x7F;
    SetEpeHeaderEditCtl(V, logOnDiscard_f, ds, val);
    SetEpeHeaderEditCtl(V, rxEtherOamCritical_f, ds, 0);
    SetEpeHeaderEditCtl(V, stackingEn_f, ds, 0);
    SetEpeHeaderEditCtl(V, evbTpid_f, ds, 0);
    SetEpeHeaderEditCtl(V, muxLengthTypeEn_f, ds, 1);
    SetEpeHeaderEditCtl(V, loopbackUseSourcePort_f, ds, 0);
    SetEpeHeaderEditCtl(V, srcVlanInfoEn_f, ds, 1);
    SetEpeHeaderEditCtl(V, chipId_f, ds, lgchip);

    SetEpeHeaderEditCtl(V, oamDestId_f, ds, SYS_RSV_PORT_OAM_CPU_ID);
    SetEpeHeaderEditCtl(V, oam_0_oamDestId_f, ds, SYS_RSV_PORT_OAM_CPU_ID);
    SetEpeHeaderEditCtl(V, oam_1_oamDestId_f, ds, SYS_RSV_PORT_OAM_CPU1_ID);
    SetEpeHeaderEditCtl(V, oamTsMacEditEn_f, ds, 1);

    SetEpeHeaderEditCtl(V, cidHdrEtherType_f, ds, 0x8909);
    SetEpeHeaderEditCtl(V, cidHdrVersion_f, ds, 1);
    SetEpeHeaderEditCtl(V, cidHdrLength_f, ds, 1);
    SetEpeHeaderEditCtl(V, cidOptionLen_f, ds, 0);
    SetEpeHeaderEditCtl(V, cidOptionType_f, ds, 1);
    SetEpeHeaderEditCtl(V, skipSpanPacketLoop_f, ds, 1);
    SetEpeHeaderEditCtl(V, discardPacketBypassEdit_f, ds, 1);
    SetEpeHeaderEditCtl(V, discardPacketLengthRecover_f, ds, 1);

    SetEpeHeaderEditCtl(V, forceHeaderCarryPortMode_f, ds, 0);
    SetEpeHeaderEditCtl(V, loopbackPktPermitIpfix_f, ds, 0);
    SetEpeHeaderEditCtl(V, e2iLoopPktPermitIpfix_f, ds, 0);
    SetEpeHeaderEditCtl(V, packetHeaderEnPktPermitIpfix_f, ds, 0);
    SetEpeHeaderEditCtl(V, loopbackPktPermitMfp_f, ds, 0);
    SetEpeHeaderEditCtl(V, e2iLoopPktPermitMfp_f, ds, 0);
    SetEpeHeaderEditCtl(V, packetHeaderEnPktPermitMfp_f, ds, 0);
    SetEpeHeaderEditCtl(V, cFlexAclDscapValidMode_f, ds, 1);    /*TMM*/
    SetEpeHeaderEditCtl(V, cFlexSrcDscapValidMode_f, ds, 1);    /*TMM*/
    SetEpeHeaderEditCtl(V, localPhyPortMax_f, ds, MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP) - 1);    /*TMM*/
    SetEpeHeaderEditCtl(V, fromCpuOrOamEn_f, ds, 1);
    SetEpeHeaderEditCtl(V, sniffingEn_f, ds, DRV_FROM_AT(lchip)?1:0);
    SetEpeHeaderEditCtl(V, loopPktSupportSniffingEn_f, ds, 1);

    SetEpeHeaderEditCtl(V, spanPktUseSrcPort_f, ds, 1);
    cmd = DRV_IOW(EpeHeaderEditCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));


    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(EpePktProcCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetEpePktProcCtl(V, discardRouteTtl0_f, ds, 1);
    SetEpePktProcCtl(V, discardMplsTtl0_f, ds, 1);
    SetEpePktProcCtl(V, discardMplsTagTtl0_f, ds, 1);
    SetEpePktProcCtl(V, discardTunnelTtl0_f, ds, 1);
    SetEpePktProcCtl(V, discardTrillTtl0_f, ds, 1);
    SetEpePktProcCtl(V, useGlobalCtagCos_f, ds, 0);
    SetEpePktProcCtl(V, mirrorEscapeCamEn_f, ds, 0);
    SetEpePktProcCtl(V, mplsDeriveLabelDisable_f, ds, 1);
    SetEpePktProcCtl(V, icmpErrMsgCheckEn_f, ds, 1);
    SetEpePktProcCtl(V, globalCtagCos_f, ds, 0);
    SetEpePktProcCtl(V, ptMulticastAddressEn_f, ds, 0);
    SetEpePktProcCtl(V, ptUdpChecksumZeroDiscard_f, ds, 1);
    SetEpePktProcCtl(V, nextHopStagCtlEn_f, ds, 1);
    SetEpePktProcCtl(V, mplsDeriveLabelDisable_f, ds, 1);
    /*-TBD  SetEpePktProcCtl(V, mplsStatsMode_f, ds, 2);*/
    SetEpePktProcCtl(V, ipIdIncreaseType_f, ds, 0);
    SetEpePktProcCtl(V, ecnIgnoreCheck_f, ds, 0); /*ECN mark enable*/
    SetEpePktProcCtl(V, ucastTtlFailExceptionEn_f, ds, 1);
    SetEpePktProcCtl(V, mcastTtlFailExceptionEn_f, ds, 1);
    SetEpePktProcCtl(V, oamTtlOne_f, ds, 1);
    SetEpePktProcCtl(V, pwPipeTtlObeyOam_f, ds, 1);
    SetEpePktProcCtl(V, lspPipeTtlObeyOam_f, ds, 1);
    SetEpePktProcCtl(V, spmePipeTtlObeyOam_f, ds, 1);
    SetEpePktProcCtl(V, oamUseLspMapTtlMode_f, ds, 0);
    SetEpePktProcCtl(V, l4PtpUdpChksumForceZero_f, ds, 1);/*TMM bit0:ipv4 bit1:ipv6*/
    SetEpePktProcCtl(V, bridgeOperationMapping_f, ds, 0xC);/*default : op_bridge_inner  will disable port check  for to Stacking header*/
    SetEpePktProcCtl(V, ipv4FlexTunnelUpdateL3Type_f, ds, 1);
    SetEpePktProcCtl(V, ipv6FlexTunnelUpdateL3Type_f, ds, 1);
    SetEpePktProcCtl(V, ipv4FlexTunnelUpdateL4Type_f, ds, 1);
    SetEpePktProcCtl(V, ipv4FlexTunnelUpdateL4TypeValue_f, ds, 0);
    SetEpePktProcCtl(V, ipv6FlexTunnelUpdateL4Type_f, ds, 1);
    SetEpePktProcCtl(V, ipv6FlexTunnelUpdateL4TypeValue_f, ds, 0);

    SetEpePktProcCtl(V, prUdfUseFlexHdrUpdateUdfIndex_f, ds, 0);/*TMM...*/
    SetEpePktProcCtl(V, glbIpTosMask_f, ds, 0xFF);
    SetEpePktProcCtl(V, sr6ReducedMode_f, ds, 1);/*TMM...*/
    SetEpePktProcCtl(V, routeIpToBridge_f, ds, 1);
    SetEpePktProcCtl(V, flexEditPktDelMax_f, ds, 0xFF);/*TMM...*/
    SetEpePktProcCtl(V, l2EtherTypeCtlSel_f, ds, 1);/*TMM...*/
    SetEpePktProcCtl(V, ofTtlFailDiscard_f, ds, 1);
    SetEpePktProcCtl(V, oamTsMacEditEn_f, ds, 1);
    SetEpePktProcCtl(V, vlanPortOverwriteXlate_f, ds, 1);
    SetEpePktProcCtl(V, vlanPortOverwriteNhp_f, ds, 1);

    CTC_BMP_SET(discard_cancel_edit,EPEDISCARDTYPE_TTL_FAIL);
    CTC_BMP_SET(discard_cancel_edit,EPEDISCARDTYPE_TUNNEL_MTU_CHK_DIS);
    CTC_BMP_SET(discard_cancel_edit,EPEDISCARDTYPE_INTERF_MTU_CHK_DIS);
    SetEpePktProcCtl(A, discardPacketCancelEditing0_f, ds, discard_cancel_edit);/*TMM...*/
    SetEpePktProcCtl(A, discardPacketCancelEditing1_f, ds, discard_cancel_edit);/*TMM...*/
    SetEpePktProcCtl(V, ipIdIncreaseStep_f, ds, 8);/*AT, bug118925*/
    cmd = DRV_IOW(EpePktProcCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    if (DRV_FROM_AT(lchip))
    {
        uint8 lchip_tmp = 0;
        uint8 lchip_start = SYS_PP_BASE(lchip);
        uint8 lchip_end = lchip_start + SYS_PP_NUM(lchip);
        sal_memset(ds, 0, sizeof(ds));
        cmd = DRV_IOW(EpeL3Ipv4IdCtl_t, DRV_ENTRY_FLAG);
        for (lchip_tmp = lchip_start; lchip_tmp < lchip_end; lchip_tmp++)
        {
            SetEpeL3Ipv4IdCtl(V, g_0_ipIdentification_f, ds, lchip_tmp);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip_tmp, 0, DRV_CMD_PP_EN(cmd), ds));
        }
    }

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(EpeXEditCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetEpeXEditCtl(V, flexEditPktDelMax_f, ds, 0xFF);/*AT...*/
    cmd = DRV_IOW(EpeXEditCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    sal_memset(mac_da, 0, sizeof(hw_mac_addr_t));
    cmd = DRV_IOR(DsEgressPortMac_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetDsEgressPortMac(A, portMac_f, ds, mac_da);
    cmd = DRV_IOW(DsEgressPortMac_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
 /*TBD*/
#if 0
    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(EpeClassificationCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetEpeClassificationCtl(V, portPolicerBase_f, ds, 0);
    cmd = DRV_IOW(EpeClassificationCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
#endif
    field_val = 48;
    cmd = DRV_IOW(EpeGlobalChannelMap_t, EpeGlobalChannelMap_maxNetworkPortChannel_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(EpeAclQosCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetEpeAclQosCtl(V, oamObeyAclDiscard_f, ds, 0x1);
    SetEpeAclQosCtl(V, reservedCategoryId_f, ds, CTC_ACL_DEFAULT_CID);  /*AT*/
    cmd = DRV_IOW(EpeAclQosCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(FibEngineLookupResultCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetFibEngineLookupResultCtl(V, gMacSaLookupResultCtl_defaultEntryEn_f, ds, 1);
    SetFibEngineLookupResultCtl(V, gMacSaLookupResultCtl_defaultEntryBase_f, ds, 0);
    SetFibEngineLookupResultCtl(V, gMacDaLookupResultCtl_defaultEntryEn_f, ds, 1);
    SetFibEngineLookupResultCtl(V, gMacDaLookupResultCtl_defaultEntryBase_f, ds, 0);
    SetFibEngineLookupResultCtl(V, gIpv4UcastLookupResultCtl_defaultEntryEn_f, ds, 1);
    SetFibEngineLookupResultCtl(V, gIpv4UcastLookupResultCtl_defaultEntryBase_f, ds, 12);
    SetFibEngineLookupResultCtl(V, gIpv4McastLookupResultCtl_defaultEntryEn_f, ds, 1);
    SetFibEngineLookupResultCtl(V, gIpv4McastLookupResultCtl_defaultEntryBase_f, ds, 13);
    SetFibEngineLookupResultCtl(V, gIpv6UcastLookupResultCtl_defaultEntryEn_f, ds, 1);
    SetFibEngineLookupResultCtl(V, gIpv6UcastLookupResultCtl_defaultEntryBase_f, ds, 14);
    SetFibEngineLookupResultCtl(V, gIpv6McastLookupResultCtl_defaultEntryEn_f, ds, 1);
    SetFibEngineLookupResultCtl(V, gIpv6McastLookupResultCtl_defaultEntryBase_f, ds, 15);
    SetFibEngineLookupResultCtl(V, gIpv4RpfLookupResultCtl_defaultEntryEn_f, ds, 1);
    SetFibEngineLookupResultCtl(V, gIpv4RpfLookupResultCtl_defaultEntryBase_f, ds, 12);
    SetFibEngineLookupResultCtl(V, gIpv6RpfLookupResultCtl_defaultEntryEn_f, ds, 1);
    SetFibEngineLookupResultCtl(V, gIpv6RpfLookupResultCtl_defaultEntryBase_f, ds, 14);
    SetFibEngineLookupResultCtl(V, gFcoeDaLookupResultCtl_defaultEntryEn_f, ds, 1);
    SetFibEngineLookupResultCtl(V, gFcoeDaLookupResultCtl_defaultEntryPtr_f, ds, 1536);
    SetFibEngineLookupResultCtl(V, gFcoeSaLookupResultCtl_defaultEntryEn_f, ds, 1);
    SetFibEngineLookupResultCtl(V, gFcoeSaLookupResultCtl_defaultEntryPtr_f, ds, 1600);
    SetFibEngineLookupResultCtl(V, gTrillUcastLookupResultCtl_defaultEntryEn_f, ds, 1);
    SetFibEngineLookupResultCtl(V, gTrillUcastLookupResultCtl_defaultEntryPtr_f, ds, 1792);
    SetFibEngineLookupResultCtl(V, gTrillMcastLookupResultCtl_defaultEntryEn_f, ds, 1);
    SetFibEngineLookupResultCtl(V, gTrillMcastLookupResultCtl_defaultEntryPtr_f, ds, 1856);
    cmd = DRV_IOW(FibEngineLookupResultCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    if (!DRV_FROM_AT(lchip))
    {
        uint32 source_chip_discard[4] = {0};
        sal_memset(ds, 0, sizeof(ds));
        cmd = DRV_IOR(BufferStoreCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetBufferStoreCtl(V, chipId_f, ds, lgchip);
        SetBufferStoreCtl(V, mcastMetFifoEnable_f, ds, 1);
        SetBufferStoreCtl(V, cpuRxExceptionEn0_f, ds, 0);
        SetBufferStoreCtl(V, cpuRxExceptionEn1_f, ds, 0);
        SetBufferStoreCtl(V, cpuTxExceptionEn_f, ds, 0);

        SetBufferStoreCtl(V, e2iErrorDiscardCtl_f, ds, 0x7FFF);
        /*except errorCode:
          E2ILOOPERROR_DOT1AE_DECRYPT_CIPHER_MODE_MISMATCH:0xa -1
          E2ILOOPERROR_DOT1AE_DECRYPT_ICV_CHECK_ERROR:0x9 -1    */
        SetBufferStoreCtl(V, e2iErrorExceptionCtl_f, ds, 0x7CFF);

        SetBufferStoreCtl(V, mplsOfModeEnable_f, ds, 1);
        SetBufferStoreCtl(V, spanPktBypassSrcCheckDisable_f, ds, 0);
        SetBufferStoreCtl(V, hmacFailDiscardEn_f, ds, 1);
        SetBufferStoreCtl(V, hmacFailExceptionEn_f, ds, 1);
        SetBufferStoreCtl(V, hmacFailExceptionSubIndex_f, ds, 56);  /*SYS_NORMAL_EXCP_SUB_TYPE_HMAC_CHECK*/
        /*set defatul value same as hw*/
        SetBufferStoreCtl(V, cpuRxQueueModeEn_f, ds, 1);
        //SetBufferStoreCtl(V, cutThroughSopLength_f, ds, 0x121);
        SetBufferStoreCtl(A, discardSourceChip_f, ds, source_chip_discard);
        SetBufferStoreCtl(V, elogChannelId_f, ds, MCHIP_CAP(SYS_CAP_CHANID_ELOG));

        /*set met fifo select*/
        SetBufferStoreCtl(V, metFifoPriMode_f, ds, 1);
        SetBufferStoreCtl(V, spanPacketToLowMetFifo_f, ds, 1);
        SetBufferStoreCtl(V, toCpuExcpPacketToHighMetFifo_f, ds, 1);
        SetBufferStoreCtl(V, macUnknownToLowMetFifo_f, ds, 1);
        cmd = DRV_IOW(BufferStoreCtl_t, DRV_ENTRY_FLAG);
        SYS_SET_TBL_ALL_DP(lchip, cmd, ds);
    }
    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(BufferRetrieveCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
     /*-TBD SetBufferRetrieveCtl(V, colorMapEn_f, ds, 0);*/
     /*-TBD SetBufferRetrieveCtl(V, chipId_f, ds, lgchip);*/
    cmd = DRV_IOW(BufferRetrieveCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(QWriteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetQWriteCtl(V, chipId_f, ds, lgchip);
    SetQWriteCtl(V, loopbackFromFabricDisable_f, ds, 0);
    SetQWriteCtl(V, cfgSingleBufferUnit_f, ds, 432);
    cmd = DRV_IOW(QWriteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    cmd = DRV_IOR(UcQWriteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetUcQWriteCtl(V, chipId_f, ds, lgchip);
    SetUcQWriteCtl(V, loopbackFromFabricDisable_f, ds, 0);
    cmd = DRV_IOW(UcQWriteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    cmd = DRV_IOR(McQWriteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetMcQWriteCtl(V, chipId_f, ds, lgchip);
    SetMcQWriteCtl(V, loopbackFromFabricDisable_f, ds, 0);
    cmd = DRV_IOW(McQWriteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(LagEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetLagEngineCtl(V, chipId_f, ds, lgchip);

    SetLagEngineCtl(V, chanOrCflexSlbHashValBasedOnIngrPortMode_f, ds, 0);
    SetLagEngineCtl(V, chanRrProtectDisable_f, ds, 0);
    SetLagEngineCtl(V, useLoopBackHashCfgEn_f, ds, 0);
    SetLagEngineCtl(V, hashOffsetForSlbNonUcPortLag_f, ds, 0);
    SetLagEngineCtl(V, hashOffsetNonUcCflexLag_f, ds, 0);
    SetLagEngineCtl(V, hashOffsetNonUcChanLag_f, ds, 0);
    SetLagEngineCtl(V, hashSelectForLoopback_f, ds, 0);
    SetLagEngineCtl(V, hashSelectForSlbNonUcPortLag_f, ds, 0);
    SetLagEngineCtl(V, hashOffsetForSlbNonUcPortLag_f, ds, 0);
    SetLagEngineCtl(V, nonUcCflexLagHashSelectGlobalCtlEn_f, ds, 0);
    SetLagEngineCtl(V, nonUcChanLagHashSelectGlobalCtlEn_f, ds, 0);
    SetLagEngineCtl(V, nonUcPortLagHashSelectGlobalCtlEn_f, ds, 0);
    SetLagEngineCtl(V, portLagIloopUseGlobalHashCfgEn_f, ds, 0);
    SetLagEngineCtl(V, portSlbHashValBasedOnIngrPortMode_f, ds, 0);
    SetLagEngineCtl(V, useLoopBackHashCfgEn_f, ds, 0);

    cmd = DRV_IOW(LagEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    /*bug32120*/
    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOW(OamUpdateCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), ds));
    cmd = DRV_IOW(DsBfdV6Addr_t, DRV_ENTRY_FLAG);
    sys_usw_ftm_query_table_entry_num(lchip, DsBfdV6Addr_t, &max_index);
    for (i = 0; i < max_index; i++)
    {
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, i, cmd, ds));
    }
    sys_usw_ftm_query_table_entry_num(lchip, DsPortProperty_t, &max_index);
    cmd = DRV_IOW(DsPortProperty_t, DRV_ENTRY_FLAG);
    for (i = 0; i < max_index; i++)
    {
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, i, cmd, ds));
    }

    field_val = 2;   /*DMA unit 16bytes, so 16 << 2 = 64*/
    cmd = DRV_IOW(BufferRetrieveCtl_t, BufferRetrieveCtl_truncationLenShift_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    field_val = 1;
    cmd = DRV_IOW(EpeHeaderEditCtl_t, EpeHeaderEditCtl_networkCpuTruncationMode_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    field_val = 1;
    cmd = DRV_IOW(EpeHeaderEditCtl_t, EpeHeaderEditCtl_networkCpuAdjustTunnel_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    field_val = 6;   /*1<<6 = 64*/
    cmd = DRV_IOW(EpeHeaderEditCtl_t, EpeHeaderEditCtl_cpuTruncationShift_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    cmd = DRV_IOR(EpeHdrAdjustCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetEpeHdrAdjustCtl(V, toCpuRecoverTruncation_f, ds, 1);
    SetEpeHdrAdjustCtl(V, bypassEpeToCpuRecoverTruncation_f, ds, 1);
    SetEpeHdrAdjustCtl(V, bypassEpeSupportTruncate_f, ds, 7);
    cmd = DRV_IOW(EpeHdrAdjustCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    if (DRV_IS_DUET2(lchip))
    {
        field_val = 1;
        cmd = DRV_IOW(DmaPktRxDropCfg_t, DmaPktRxDropCfg_cfgPktRxTruncEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    }

    sal_memset(&net_tx_truncate_en_ctl, 0, sizeof(NetTxTruncateEnableCtl_m));
    sal_memset(truncate_en, 0xFF, 5*sizeof(uint32));
    SetNetTxTruncateEnableCtl(A, truncateEn_f, &net_tx_truncate_en_ctl, truncate_en);
    cmd = DRV_IOW(NetTxTruncateEnableCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &net_tx_truncate_en_ctl));
    if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
    {
        cmd = DRV_IOW(NetTxTruncateEnableCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 1, cmd, &net_tx_truncate_en_ctl));
    }
    /*Eco*/
    if (DRV_IS_DUET2(lchip))
    {

        field_val = 3;
        cmd = DRV_IOW(IpeFwdReserved_t, IpeFwdReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    }
    /**< [TM] START */
    field_val = 1;
    cmd = DRV_IOW(IpeAclQosCtl_t, IpeAclQosCtl_fromCpuOrOamBypassPolicing_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    cmd = DRV_IOW(IpeAclQosCtl_t, IpeAclQosCtl_fromCpuOrOamBypassStorm_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    /**< [TM] END */
    if (DRV_IS_DUET2(lchip))
    {
        field_val = 1;
        cmd = DRV_IOW(EpeAclOamReserved_t, EpeAclOamReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        field_val = 1;
        cmd = DRV_IOW(IpePktProcReserved_t, IpePktProcReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    }
    field_val = 1;
    cmd = DRV_IOW(ErmMiscCtl_t, ErmMiscCtl_scExcludeGuarantee_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    field_val = DRV_IS_DUET2(lchip) ? 1 : 0;
    cmd = DRV_IOW(IpeIntfMapReserved_t, IpeIntfMapReserved_reserved_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd , &field_val));

    field_val = 2;
    cmd = DRV_IOW(IpeCapwapFragCtl_t, IpeCapwapFragCtl_fragTableMgrMode_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    /* cfg iloop use default index 7 to check pkt length*/
    if (DRV_IS_DUET2(lchip))
    {
        field_val = CTC_FRAME_SIZE_7;
        cmd = DRV_IOW(NetRxMiscChanPktLenChkCtl_t, NetRxMiscChanPktLenChkCtl_cfgMiscMinLenSelId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 11, cmd, &field_val));

        field_val = CTC_FRAME_SIZE_7;
        cmd = DRV_IOW(NetRxMiscChanPktLenChkCtl_t, NetRxMiscChanPktLenChkCtl_cfgMiscMaxLenSelId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 11, cmd, &field_val));
    }
    else
    {
        field_val = SYS_USW_ILOOP_MIN_FRAMESIZE_DEFAULT_VALUE;
        cmd = DRV_IOW(NetRxMiscChanPktLenChkCtl_t, NetRxMiscChanPktLenChkCtl_cfgMiscMinLen_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 11, cmd, &field_val));

        field_val = MCHIP_CAP(SYS_CAP_PORT_MAX_FRAMESIZE_MAX_VALUE);
        cmd = DRV_IOW(NetRxMiscChanPktLenChkCtl_t, NetRxMiscChanPktLenChkCtl_cfgMiscMaxLen_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 11, cmd, &field_val));
    }

#if (SDK_WORK_PLATFORM == 1)
    field_val = 1;
    cmd = DRV_IOW(FibAccelerationSliceModeCtl_t, FibAccelerationSliceModeCtl_iAmMaster_f);
    cmd = DRV_CMD_SID(cmd, 0);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
#endif

    sal_memset(ds, 0, sizeof(ds));/*MUST update _sys_usw_nh_map_ether_type!!!*/
    SetEpeL2EtherTypeCtl(V, g_0_etherType_f,  ds, 0);   /*L3TYPE_NONE      */
    SetEpeL2EtherTypeCtl(V, g_1_etherType_f,  ds, 0x0800);   /*L3TYPE_IP        */
    SetEpeL2EtherTypeCtl(V, g_2_etherType_f,  ds, 0x0800);   /*L3TYPE_IPV4      */
    SetEpeL2EtherTypeCtl(V, g_3_etherType_f,  ds, 0x86DD);   /*L3TYPE_IPV6      */
    SetEpeL2EtherTypeCtl(V, g_4_etherType_f,  ds, 0x8847);   /*L3TYPE_MPLS      */
    SetEpeL2EtherTypeCtl(V, g_5_etherType_f,  ds, 0x8848);   /*L3TYPE_MPLSUP    */
    SetEpeL2EtherTypeCtl(V, g_6_etherType_f,  ds, 0x0806);   /*L3TYPE_ARP       */
    SetEpeL2EtherTypeCtl(V, g_7_etherType_f,  ds, 0x8906);   /*L3TYPE_FCOE      */
    SetEpeL2EtherTypeCtl(V, g_8_etherType_f,  ds, 0x22F3);   /*L3TYPE_TRILL     */
    SetEpeL2EtherTypeCtl(V, g_9_etherType_f,  ds, 0x8902);   /*L3TYPE_ETHEROAM  */
    SetEpeL2EtherTypeCtl(V, g_10_etherType_f,ds, 0x8809);    /*L3TYPE_SLOWPROTO */
    SetEpeL2EtherTypeCtl(V, g_11_etherType_f,ds, 0x894F);    /*L3TYPE_NSH       */
    SetEpeL2EtherTypeCtl(V, g_12_etherType_f,ds, 0x88F7);   /*L3TYPE_PTP       */
    SetEpeL2EtherTypeCtl(V, g_13_etherType_f,ds, 0x88E5);   /*L3TYPE_DOT1AE    */
    SetEpeL2EtherTypeCtl(V, g_14_etherType_f,ds, 0x88B7);   /*L3TYPE_SATPDU    */
    SetEpeL2EtherTypeCtl(V, g_15_etherType_f,ds, 0);   /*L3TYPE_FLEXIBLE  */
    cmd = DRV_IOW(EpeL2EtherTypeCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    cmd = DRV_IOW(EpeInnerL2EtherTypeCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(GlobalChannelIdReg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetGlobalChannelIdReg(V, loopChannel0_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_ELOG));
    SetGlobalChannelIdReg(V, loopChannel1_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_ELOOP));
    SetGlobalChannelIdReg(V, loopChannel2_f,  ds, DRV_IS_TMG(lchip) ? MCHIP_CAP(SYS_CAP_CHANID_RSV) : (MCHIP_CAP(SYS_CAP_CHANID_ELOOP)+2));
    SetGlobalChannelIdReg(V, loopChannel3_f,  ds, SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_ELOOP)+MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM)));
    SetGlobalChannelIdReg(V, loopChannel4_f,  ds, DRV_IS_TMG(lchip) ? MCHIP_CAP(SYS_CAP_CHANID_RSV) : (MCHIP_CAP(SYS_CAP_CHANID_ELOOP)+2+MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM)));
    SetGlobalChannelIdReg(V, loopChannel5_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
    SetGlobalChannelIdReg(V, loopChannel6_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
    SetGlobalChannelIdReg(V, loopChannel7_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
    SetGlobalChannelIdReg(V, cpuChannel0_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC0));
    SetGlobalChannelIdReg(V, cpuChannel1_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC1));
    SetGlobalChannelIdReg(V, cpuChannel2_f,  ds, SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC2)));
    SetGlobalChannelIdReg(V, cpuChannel3_f,  ds, SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC3)));
    SetGlobalChannelIdReg(V, cpuChannel4_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
    SetGlobalChannelIdReg(V, cpuChannel5_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
    SetGlobalChannelIdReg(V, cpuChannel6_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
    SetGlobalChannelIdReg(V, cpuChannel7_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
    SetGlobalChannelIdReg(V, dmaChannel0_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_DMA_RX0));
    SetGlobalChannelIdReg(V, dmaChannel1_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_DMA_RX1));
    SetGlobalChannelIdReg(V, dmaChannel2_f,  ds, SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_DMA_RX2)));
    SetGlobalChannelIdReg(V, dmaChannel3_f,  ds, SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_DMA_RX3)));
    SetGlobalChannelIdReg(V, dmaChannel4_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_DMA_RX0));
    SetGlobalChannelIdReg(V, dmaChannel5_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_DMA_RX1));
    SetGlobalChannelIdReg(V, dmaChannel6_f,  ds, SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_DMA_RX2)));
    SetGlobalChannelIdReg(V, dmaChannel7_f,  ds, SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_DMA_RX3)));

#ifdef __TODO__
    SetGlobalChannelIdReg(V, dmaEventChannel_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
#endif
    SetGlobalChannelIdReg(V, oamChannel0_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_OAM));
    SetGlobalChannelIdReg(V, oamChannel1_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_OAM));

    cmd = DRV_IOW(GlobalChannelIdReg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    cmd = DRV_IOW(GlobalChannelIdRegFwd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
#ifndef EMULATION_ENV
    if (!DRV_FROM_AT(lchip))
    {
        cmd = DRV_IOW(GlobalChannelIdRegAclOam_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    }
#endif
    sal_memset(ds, 0, sizeof(ds));
    SetEpeHeaderEditBypassCfg(V, elogBypassIpe_f,  ds, 0x7FFF);
    cmd = DRV_IOW(EpeHeaderEditBypassCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    if (DRV_FROM_TMM(lchip))
    {
        uint8 cpumac_net_en_tmp = 0;
        uint8 cpumac_net_en[4] = {0};
        uint32 chan_id[4] = {0};
        uint8 gchip = 0;
        uint16 lport = 0;
        uint32 value[CTC_PORT_BITMAP_IN_WORD] = {0};
        field_val = SYS_RSV_PORT_TO_CPU;
        cmd = DRV_IOW(EpeHeaderAdjustPhyPortMap_t, EpeHeaderAdjustPhyPortMap_localPhyPort_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, MCHIP_CAP(SYS_CAP_CHANID_DMA_RX0), cmd, &field_val));
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, MCHIP_CAP(SYS_CAP_CHANID_DMA_RX1), cmd, &field_val));
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, MCHIP_CAP(SYS_CAP_CHANID_DMA_RX2), cmd, &field_val));
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, MCHIP_CAP(SYS_CAP_CHANID_DMA_RX3), cmd, &field_val));
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC0), cmd, &field_val));
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC1), cmd, &field_val));
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC2), cmd, &field_val));
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC3), cmd, &field_val));

        sal_memset(ds, 0, sizeof(ds));
        SetEpeScheduleMinPktLenCfg(V, toMiscMinPktLen_f,  ds, 0);
        SetEpeScheduleMinPktLenCfg(V, toNetMinPktLen_f,  ds, 0);
        cmd = DRV_IOW(EpeScheduleMinPktLenCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        if (!DRV_FROM_AT(lchip))
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(1, 0), cmd, ds));
        }
        CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));
        if (MCHIP_DMPS(lchip)->cpumac_get_lport_info_by_inner_idx)
        {
            cmd = DRV_IOR(EpeHeaderAdjustBypassCfg_t,DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            GetEpeHeaderAdjustBypassCfg(A,bypassEpe_f,ds,value);
            for (i = 0; i < SYS_USW_CPU_MAC_NUM; i++)
            {
                ret = MCHIP_DMPS(lchip)->cpumac_get_lport_info_by_inner_idx(lchip,i,&lport,&cpumac_net_en_tmp);
                dmps_port_info.gport = CTC_MAP_LPORT_TO_GPORT(gchip,lport);               
                cpumac_net_en[i] = cpumac_net_en_tmp;
                if(lport >= MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP))
                {
                    chan_id[i] = SYS_COMMON_USELESS_CHANNEL;
                    continue;
                }
                CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id[i]));
                if (!cpumac_net_en[i])
                {
                    CTC_BIT_SET(value[lport / 32], (lport % 32));
                }
                else
                {
                    CTC_BIT_UNSET(value[lport / 32], (lport % 32));
                }
            }
            SetEpeHeaderAdjustBypassCfg(A, bypassEpe_f, ds, value);
            cmd = DRV_IOW(EpeHeaderAdjustBypassCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        }

        if (!DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOR(NetRxCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            SetNetRxCtl(V, cfgCpuMacIsNet_f, ds, (cpumac_net_en[0] || cpumac_net_en[1])?1:0);
            cmd = DRV_IOW(NetRxCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(1, 0), cmd, ds));

            SetNetRxCtl(V, cfgCpuMacIsNet_f, ds, (cpumac_net_en[0] || cpumac_net_en[1])?1:0);
            cmd = DRV_IOW(NetRxCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

            cmd = DRV_IOR(NetRxCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(1, 0), cmd, ds));
            SetNetRxCtl(V, cfgCpuMacIsNet_f, ds, (cpumac_net_en[2] || cpumac_net_en[3])? 1 : 0);
            cmd = DRV_IOW(NetRxCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(1, 0), cmd, ds));

            cmd = DRV_IOR(EpeScheduleSaturationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            SetEpeScheduleSaturationCtl(V, cfgCpuMacIsNetworkEn_f, ds, (cpumac_net_en[0] || cpumac_net_en[1])?3:0);
            cmd = DRV_IOW(EpeScheduleSaturationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

            cmd = DRV_IOR(NetRxMiscChanIdCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            SetNetRxMiscChanIdCfg(V, cfgCpuMacChanId0_f, ds,chan_id[0]);
            SetNetRxMiscChanIdCfg(V, cfgCpuMacChanId1_f, ds,chan_id[1]);
            cmd = DRV_IOW(NetRxMiscChanIdCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));


            cmd = DRV_IOR(EpeScheduleSaturationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(1, 0), cmd, ds));
            SetEpeScheduleSaturationCtl(V, cfgCpuMacIsNetworkEn_f, ds, (cpumac_net_en[2] || cpumac_net_en[3])? 3 : 0);
            cmd = DRV_IOW(EpeScheduleSaturationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(1, 0), cmd, ds));

            cmd = DRV_IOR(NetRxMiscChanIdCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(1, 0), cmd, ds));
            SetNetRxMiscChanIdCfg(V, cfgCpuMacChanId0_f, ds, (chan_id[2] - MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM)));
            SetNetRxMiscChanIdCfg(V, cfgCpuMacChanId1_f, ds, (chan_id[3] - MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM)));
            cmd = DRV_IOW(NetRxMiscChanIdCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(1, 0), cmd, ds));

            cmd = DRV_IOR(CpuMacEtherTypePktEn_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            SetCpuMacEtherTypePktEn(V, etherTypePktEn0_f, ds, cpumac_net_en[0] ? 0 : 1);
            SetCpuMacEtherTypePktEn(V, etherTypePktEn1_f, ds, cpumac_net_en[1] ? 0 : 1);
            SetCpuMacEtherTypePktEn(V, etherTypePktEn2_f, ds, cpumac_net_en[2] ? 0 : 1);
            SetCpuMacEtherTypePktEn(V, etherTypePktEn3_f, ds, cpumac_net_en[3] ? 0 : 1);
            cmd = DRV_IOW(CpuMacEtherTypePktEn_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

            cmd = DRV_IOR(BufStoreProcMiscChanIdCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            SetBufStoreProcMiscChanIdCfg(V, cfgMaxNetChanId_f, ds, (cpumac_net_en[0] && cpumac_net_en[1] && cpumac_net_en[2] && cpumac_net_en[3]) ? (MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC0) - 1 + 2) : (MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC0) - 1));
            cmd = DRV_IOW(BufStoreProcMiscChanIdCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        }

        cmd = DRV_IOR(IpeHdrAdjChanCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetIpeHdrAdjChanCfg(V, cfgCpu0ChanId_f,  ds, cpumac_net_en[0]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC0));
        SetIpeHdrAdjChanCfg(V, cfgCpu1ChanId_f,  ds, cpumac_net_en[1]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC1));
        SetIpeHdrAdjChanCfg(V, cfgCpu2ChanId_f,  ds, cpumac_net_en[2]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : (MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC2) - MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM)));
        SetIpeHdrAdjChanCfg(V, cfgCpu3ChanId_f,  ds, cpumac_net_en[3]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : (MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC3) - MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM)));
        cmd = DRV_IOW(IpeHdrAdjChanCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

        cmd = DRV_IOR(EpeHdrProcChanIdCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetEpeHdrProcChanIdCfg(V, cpuChannel0_f,  ds, cpumac_net_en[0]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC0));
        SetEpeHdrProcChanIdCfg(V, cpuChannel1_f,  ds, cpumac_net_en[1]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC1));
        SetEpeHdrProcChanIdCfg(V, cpuChannel2_f,  ds, cpumac_net_en[2]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC2)));
        SetEpeHdrProcChanIdCfg(V, cpuChannel3_f,  ds, cpumac_net_en[3]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC3)));
        SetEpeHdrProcChanIdCfg(V, cpuChannel4_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetEpeHdrProcChanIdCfg(V, cpuChannel5_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetEpeHdrProcChanIdCfg(V, cpuChannel6_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetEpeHdrProcChanIdCfg(V, cpuChannel7_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        cmd = DRV_IOW(EpeHdrProcChanIdCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

        cmd = DRV_IOR(QMgrQWriteChanIdCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetQMgrQWriteChanIdCfg(V, cpuChannel0_f,  ds, cpumac_net_en[0]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC0));
        SetQMgrQWriteChanIdCfg(V, cpuChannel1_f,  ds, cpumac_net_en[1]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC1));
        SetQMgrQWriteChanIdCfg(V, cpuChannel2_f,  ds, cpumac_net_en[2]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC2)));
        SetQMgrQWriteChanIdCfg(V, cpuChannel3_f,  ds, cpumac_net_en[3]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC3)));
        SetQMgrQWriteChanIdCfg(V, cpuChannel4_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetQMgrQWriteChanIdCfg(V, cpuChannel5_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetQMgrQWriteChanIdCfg(V, cpuChannel6_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetQMgrQWriteChanIdCfg(V, cpuChannel7_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        cmd = DRV_IOW(QMgrQWriteChanIdCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

        cmd = DRV_IOR(GlobalChannelIdRegFwd_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetGlobalChannelIdRegFwd(V, cpuChannel0_f,  ds, cpumac_net_en[0]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC0));
        SetGlobalChannelIdRegFwd(V, cpuChannel1_f,  ds, cpumac_net_en[1]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC1));
        SetGlobalChannelIdRegFwd(V, cpuChannel2_f,  ds, cpumac_net_en[2]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC2)));
        SetGlobalChannelIdRegFwd(V, cpuChannel3_f,  ds, cpumac_net_en[3]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC3)));
        SetGlobalChannelIdRegFwd(V, cpuChannel4_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetGlobalChannelIdRegFwd(V, cpuChannel5_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetGlobalChannelIdRegFwd(V, cpuChannel6_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetGlobalChannelIdRegFwd(V, cpuChannel7_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        cmd = DRV_IOW(GlobalChannelIdRegFwd_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        if (!DRV_FROM_AT(lchip))
          {
              cmd = DRV_IOR(GlobalChannelIdRegAclOam_t, DRV_ENTRY_FLAG);
              CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
              SetGlobalChannelIdRegAclOam(V, cpuChannel0_f,  ds, cpumac_net_en[0]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC0));
              SetGlobalChannelIdRegAclOam(V, cpuChannel1_f,  ds, cpumac_net_en[1]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC1));
              SetGlobalChannelIdRegAclOam(V, cpuChannel2_f,  ds, cpumac_net_en[2]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC2)));
              SetGlobalChannelIdRegAclOam(V, cpuChannel3_f,  ds, cpumac_net_en[3]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC3)));
              SetGlobalChannelIdRegAclOam(V, cpuChannel4_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
              SetGlobalChannelIdRegAclOam(V, cpuChannel5_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
              SetGlobalChannelIdRegAclOam(V, cpuChannel6_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
              SetGlobalChannelIdRegAclOam(V, cpuChannel7_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
              cmd = DRV_IOW(GlobalChannelIdRegAclOam_t, DRV_ENTRY_FLAG);
              CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
          }
        if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_OAM))
        {
            field_val = 1;
            cmd = DRV_IOW(OamHeaderAdjustCtl_t, OamHeaderAdjustCtl_relayAllToCpu_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        cmd = DRV_IOR(GlobalChannelIdReg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetGlobalChannelIdReg(V, cpuChannel0_f,  ds, cpumac_net_en[0]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC0) );
        SetGlobalChannelIdReg(V, cpuChannel1_f,  ds, cpumac_net_en[1]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC1) );
        SetGlobalChannelIdReg(V, cpuChannel2_f,  ds, cpumac_net_en[2]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC2)));
        SetGlobalChannelIdReg(V, cpuChannel3_f,  ds, cpumac_net_en[3]? MCHIP_CAP(SYS_CAP_CHANID_RSV) : SYS_USW_CHANNEL_ENCODE(MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC3)));
        SetGlobalChannelIdReg(V, cpuChannel4_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetGlobalChannelIdReg(V, cpuChannel5_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetGlobalChannelIdReg(V, cpuChannel6_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetGlobalChannelIdReg(V, cpuChannel7_f,  ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        cmd = DRV_IOW(GlobalChannelIdReg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    }
    
    field_val = 1;
    cmd = DRV_IOW(EpeHeaderAdjustBypassCfg_t, EpeHeaderAdjustBypassCfg_customerIdEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    cmd = DRV_IOW(IpeLearningCtl_t, IpeLearningCtl_portSecurityType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd , &field_val));
    cmd = DRV_IOR(EpeHdrAdjReserved_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    val=GetEpeHdrAdjReserved(V, reserved_f,  ds);
    val|= 1;
    SetEpeHdrAdjReserved(V, reserved_f,  ds, val);
    cmd = DRV_IOW(EpeHdrAdjReserved_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    if(DRV_FROM_TMM(lchip))
    {
        cmd = DRV_IOR(LagEngineCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetLagEngineCtl(V, rightShiftControl_f,  ds, 1);
        cmd = DRV_IOW(LagEngineCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

        cmd = DRV_IOR(IpeFwdCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_ctl));
        SetIpeFwdCtl(V, nonUcLagRightShiftControl_f,  &ipe_fwd_ctl, 1);
        SetIpeFwdCtl(V, entropyRightShiftControl_f,  &ipe_fwd_ctl, 1);
        SetIpeFwdCtl(V, ecmpRightShiftControl_f,  &ipe_fwd_ctl, 1);
        SetIpeFwdCtl(V, cflexUplinkRightShiftControl_f,  &ipe_fwd_ctl, 1);
        cmd = DRV_IOW(IpeFwdCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_ctl));
    }

    cmd = DRV_IOR(IpeFwdDiscardStatsCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeFwdDiscardStatsCtl(V, clearOnRead_f,  ds, 1);
    cmd = DRV_IOW(IpeFwdDiscardStatsCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOR(PortIsolationForwardTypeMapCtl_t, DRV_ENTRY_FLAG);/*AT_TODO :whether support api to config this*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    for( i = 0; i < 16; i++)
    {
        SetPortIsolationForwardTypeMapCtl(V, gFwdType_0_typeValue_f +i*step1,  ds, i);

    }
    cmd = DRV_IOW(PortIsolationForwardTypeMapCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    field_val = 1;
    cmd = DRV_IOW(BufferStoreCtl_t, BufferStoreCtl_ipfixMmuEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    if (DRV_FROM_AT(lchip))
    {
        XfcTimerCtlType0_m xfc_timer_ctl;
        sal_memset(ds, 0, sizeof(ds));
        sal_memset(&xfc_timer_ctl, 0, sizeof(XfcTimerCtlType0_m));

        /*destIsDma = dmaSubChanVec[{ ppId[2:0], dpId }]*/
        SetBufferStoreMiscPortCtl(V, dmaSubChanVec_f, ds, 1);
        cmd = DRV_IOW(BufferStoreMiscPortCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, (((uint64)0x7F << 32) | cmd), ds));

        SetMcQWriteMiscPortCtl(V, dmaSubChanVec_f, ds, 1);
        cmd = DRV_IOW(McQWriteMiscPortCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, (((uint64)0x7F << 32) | cmd), ds));

        if (SYS_VCHIP_DUAL_CORE_MODE(lchip))
        {
            uint8 _dual_core_lchip = 0;

            SYS_VCHIP_DUAL_CORE_LCHIP_MAP(lchip, _dual_core_lchip);

            SetBufferStoreMiscPortCtl(V, dmaSubChanVec_f, ds, 0x100);
            cmd = DRV_IOW(BufferStoreMiscPortCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL_BMP(_dual_core_lchip, 0, (((uint64)0xBF << 32) | cmd), ds));

            SetMcQWriteMiscPortCtl(V, dmaSubChanVec_f, ds, 0x100);
            cmd = DRV_IOW(McQWriteMiscPortCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, (((uint64)0xBF << 32) | cmd), ds));
        }

        SetXfcTimerCtlType0(V, xfcRefreshDis_f, &xfc_timer_ctl, 1);
        cmd = DRV_IOW(XfcTimerCtlType0_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &xfc_timer_ctl));
        cmd = DRV_IOW(XfcTimerCtlType1_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &xfc_timer_ctl));
        cmd = DRV_IOW(XfcTimerCtlType2_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &xfc_timer_ctl));


        sal_memset(ds, 0, sizeof(ds));
        cmd = DRV_IOR(EpeHeaderEditMuxCtl_t, DRV_ENTRY_FLAG);
        SetEpeHeaderEditMuxCtl(V, ctcXSecTxSelect2_f, &ds, 0);/*AT_TODO*/
        SetEpeHeaderEditMuxCtl(V, ctcXSecEcmpHashSel_f, &ds, 2);
        SetEpeHeaderEditMuxCtl(V, ctcXSecCidSel_f, &ds, 4);
        SetEpeHeaderEditMuxCtl(V, ctcXSecCidExtSel_f, &ds, 5);
        SetEpeHeaderEditMuxCtl(V, i2eSrcCidMask_f, &ds, 0xFFFF);
        cmd = DRV_IOW(EpeHeaderEditMuxCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));


        /*for cid*/
        cmd = DRV_IOR(IpeLoopbackHeaderAdjustCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetIpeLoopbackHeaderAdjustCtl(V, supportExtLenCid_f, ds, 1);
        cmd = DRV_IOW(IpeLoopbackHeaderAdjustCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

        cmd = DRV_IOR(IpeFwdCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetIpeFwdCtl(V, supportExtLenCid_f, ds, 1);
        cmd = DRV_IOW(IpeFwdCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

        cmd = DRV_IOR(EpeHdrAdjustCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetEpeHdrAdjustCtl(V, supportExtLenCid_f, ds, 1);
        cmd = DRV_IOW(EpeHdrAdjustCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

        cmd = DRV_IOR(EpeHeaderEditCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetEpeHeaderEditCtl(V, supportExtLenCid_f, ds, 1);
        SetEpeHeaderEditCtl(V, toCpuWithCidExt_f, ds, 1);
        cmd = DRV_IOW(EpeHeaderEditCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

        cmd = DRV_IOR(EpeScheduleLoopCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetEpeScheduleLoopCtl(V, cfgLogGlobalTruncEn_f, ds, 0);
        cmd = DRV_IOW(EpeScheduleLoopCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

        cmd = DRV_IOR(PGMiscCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetPGMiscCfg(V, cfgOamSliceSel_f, ds, 0);
        cmd = DRV_IOW(PGMiscCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    }
    return ret;
}


STATIC int32
_sys_usw_mpls_ctl_init(uint8 lchip)
{
    uint32 cmd = 0;
    ds_t ds;
    uint32 value = 0;

    sal_memset(ds, 0, sizeof(ds));

    if (DRV_IS_DUET2(lchip) || DRV_IS_TSINGMA(lchip))
    {
        cmd = DRV_IOW(EpeL3EditMplsTtl_t, DRV_ENTRY_FLAG);
        SetEpeL3EditMplsTtl(V, array_0_ttl_f, ds, 0);
        SetEpeL3EditMplsTtl(V, array_1_ttl_f, ds, 1);
        SetEpeL3EditMplsTtl(V, array_2_ttl_f, ds, 2);
        SetEpeL3EditMplsTtl(V, array_3_ttl_f, ds, 8);
        SetEpeL3EditMplsTtl(V, array_4_ttl_f, ds, 15);
        SetEpeL3EditMplsTtl(V, array_5_ttl_f, ds, 16);
        SetEpeL3EditMplsTtl(V, array_6_ttl_f, ds, 31);
        SetEpeL3EditMplsTtl(V, array_7_ttl_f, ds, 32);
        SetEpeL3EditMplsTtl(V, array_8_ttl_f, ds, 60);
        SetEpeL3EditMplsTtl(V, array_9_ttl_f, ds, 63);
        SetEpeL3EditMplsTtl(V, array_10_ttl_f, ds, 64);
        SetEpeL3EditMplsTtl(V, array_11_ttl_f, ds, 65);
        SetEpeL3EditMplsTtl(V, array_12_ttl_f, ds, 127);
        SetEpeL3EditMplsTtl(V, array_13_ttl_f, ds, 128);
        SetEpeL3EditMplsTtl(V, array_14_ttl_f, ds, 254);
        SetEpeL3EditMplsTtl(V, array_15_ttl_f, ds, 255);
    }
    else
    {
        cmd = DRV_IOW(EpeL3EditMplsCtl_t, DRV_ENTRY_FLAG);
        SetEpeL3EditMplsCtl(V, g_0_ttl_f, ds, 0);
        SetEpeL3EditMplsCtl(V, g_1_ttl_f, ds, 1);
        SetEpeL3EditMplsCtl(V, g_2_ttl_f, ds, 2);
        SetEpeL3EditMplsCtl(V, g_3_ttl_f, ds, 8);
        SetEpeL3EditMplsCtl(V, g_4_ttl_f, ds, 15);
        SetEpeL3EditMplsCtl(V, g_5_ttl_f, ds, 16);
        SetEpeL3EditMplsCtl(V, g_6_ttl_f, ds, 31);
        SetEpeL3EditMplsCtl(V, g_7_ttl_f, ds, 32);
        SetEpeL3EditMplsCtl(V, g_8_ttl_f, ds, 60);
        SetEpeL3EditMplsCtl(V, g_9_ttl_f, ds, 63);
        SetEpeL3EditMplsCtl(V, g_10_ttl_f, ds, 64);
        SetEpeL3EditMplsCtl(V, g_11_ttl_f, ds, 65);
        SetEpeL3EditMplsCtl(V, g_12_ttl_f, ds, 127);
        SetEpeL3EditMplsCtl(V, g_13_ttl_f, ds, 128);
        SetEpeL3EditMplsCtl(V, g_14_ttl_f, ds, 254);
        SetEpeL3EditMplsCtl(V, g_15_ttl_f, ds, 255);
    }

    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    value = 1;
    cmd = DRV_IOW(IpeMplsTtlThrd_t, IpeMplsTtlThrd_array_0_ttlThreshold_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(BufferStoreCtl_t, BufferStoreCtl_mplsOfModeEnable_f);
    SYS_SET_FIELD_TBL_ALL_DP(lchip, cmd, value);

    cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_mplsOfModeEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    if(DRV_FROM_TMM(lchip))
    {
        EpePktProcCtl_m epe_pkt_pro_ctl;
        sal_memset(&epe_pkt_pro_ctl, 0, sizeof(epe_pkt_pro_ctl));

        cmd = DRV_IOR(EpePktProcCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_pkt_pro_ctl));
        SetEpePktProcCtl(V, esLabelEncapsOnlyForMcast_f, &epe_pkt_pro_ctl, 1);    /* add eslabel only for Mc */
        SetEpePktProcCtl(V, initNodeStatsSelect_f, &epe_pkt_pro_ctl, 2);  /*  MPLS In-Band Loss Measurement, Use spme stats */
        SetEpePktProcCtl(V, fihNhdMapArray_1_fihNextHeader_f, &epe_pkt_pro_ctl, 0x01); /*  MPLS In-Band FIH Type */
        SetEpePktProcCtl(V, fihNhdMapArray_2_fihNextHeader_f, &epe_pkt_pro_ctl, 0x02);
        SetEpePktProcCtl(V, fiiLabel_f, &epe_pkt_pro_ctl, 0xC);    /*  MPLS In-Band FII */
        SetEpePktProcCtl(V, fihReserved_f, &epe_pkt_pro_ctl, 1);    /*  MPLS In-Band R/S, 1 indicate FII is sbit bottom*/
        SetEpePktProcCtl(V, globalFlexUdpTunnelEn_f, &epe_pkt_pro_ctl, 1);    /* AT */
        cmd = DRV_IOW(EpePktProcCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_pkt_pro_ctl));

        /* MPLS In-Band Delay Measurement */
        value = 1;
        cmd = DRV_IOW(IpeAclQosCtl_t, IpeAclQosCtl_dFlagStatusExceptionEn0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        cmd = DRV_IOW(IpeAclQosCtl_t, IpeAclQosCtl_dFlagStatusExceptionEn1_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

         /*  MPLS In-Band FII */
        value = 0xC;
        cmd = DRV_IOW(ParserMplsCtl_t, ParserMplsCtl_mplsInbandOamFIILabel_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        cmd = DRV_IOW(IpeMplsCtl_t, IpeMplsCtl_eliLabel_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_excp_ctl_init(uint8 lchip)
{
    /* POP DS */
    uint32 cmd = 0;
    uint32 excp_idx = 0;
    uint32 value = 0;
    uint8 gchip  = 0;
    ds_t ds;
    sys_usw_get_gchip_id(lchip, &gchip);
    sal_memset(ds, 0, sizeof(ds));
    SetDsMetFifoExcp(V, destMap_f, ds, SYS_ENCODE_DESTMAP(gchip, SYS_RSV_PORT_DROP_ID));
    cmd = DRV_IOW(DsMetFifoExcp_t, DRV_ENTRY_FLAG);
    for (excp_idx = 0; excp_idx < 320; excp_idx++)
    {
        if (DRV_FROM_AT(lchip))
        {
            sal_memset(ds, 0, sizeof(ds));
            cmd = DRV_IOW(DsMetFifoPreExcp_t, DRV_ENTRY_FLAG);
            SetDsMetFifoPreExcp(V, replicationVector_f, ds, 1);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, excp_idx, cmd, ds));
        }
        sal_memset(ds, 0, sizeof(ds));
        SetDsMetFifoExcp(V, destMap_f, ds, SYS_ENCODE_DESTMAP(gchip, SYS_RSV_PORT_DROP_ID));
        cmd = DRV_IOW(DsMetFifoExcp_t, DRV_ENTRY_FLAG);
        if (DRV_FROM_AT(lchip))
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, excp_idx << 3, cmd, ds));
        }
        else
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, excp_idx, cmd, ds));
        }
    }

    value = 1;
    cmd = DRV_FROM_TMM(lchip) ? DRV_IOW(EpeHdrAdjExcpCtl_t, EpeHdrAdjExcpCtl_exceptionEditMode_f) : DRV_IOW(BufRetrvExcpCtl_t, BufRetrvExcpCtl_exceptionEditMode_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    if(DRV_FROM_AT(lchip))
    {
        cmd = DRV_IOW(EpeHdrAdjExcpCtl_t, EpeHdrAdjExcpCtl_fwdUseExcpEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }
    value = 0;
    cmd = DRV_FROM_TMM(lchip) ? DRV_IOW(EpeHdrAdjExcpCtl_t, EpeHdrAdjExcpCtl_cflexExcepRestOffsetSkipCfHdr_f) : DRV_IOW(BufRetrvExcpCtl_t, BufRetrvExcpCtl_cflexExcepRestOffsetSkipCfHdr_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    return CTC_E_NONE;
}

#if 0
STATIC int32
_sys_usw_net_rx_tx_init(uint8 lchip)
{
    return CTC_E_NONE;
}
#endif

STATIC int32
_sys_usw_ipe_loopback_hdr_adjust_ctl_init(uint8 lchip)
{
    uint32 cmd = 0;
    ds_t ds_data;
    uint32 field_val = 0;

    cmd = DRV_IOR(IpeLoopbackHeaderAdjustCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds_data));

    SetIpeLoopbackHeaderAdjustCtl(V, iloopFromCpuBypassAll_f, ds_data, 1);
    SetIpeLoopbackHeaderAdjustCtl(V, loopbackInternalPortBaseValid0_f, ds_data, 0);
    SetIpeLoopbackHeaderAdjustCtl(V, loopbackInternalPortBaseValid1_f, ds_data, 0);
    SetIpeLoopbackHeaderAdjustCtl(V, iloopDisableSourceHashInfo_f, ds_data, 0);
    SetIpeLoopbackHeaderAdjustCtl(V, iloopFromCpuDisableSourceHashInfo_f, ds_data, 0);
    SetIpeLoopbackHeaderAdjustCtl(V, loopbackFromFabricEn_f, ds_data, 0);
    SetIpeLoopbackHeaderAdjustCtl(V, alwaysUseHeaderLogicPort_f, ds_data, 1);
    SetIpeLoopbackHeaderAdjustCtl(V, iloopVrfidEn_f, ds_data, 0);  /* This field MUST be set 0. Asic not supports that outer vrfid covers inner vrfid.*/
    SetIpeLoopbackHeaderAdjustCtl(V, internalPortBase_f, ds_data, 0);
    SetIpeLoopbackHeaderAdjustCtl(V, loopbackClearSrcCidValidEn_f, ds_data, 1);
    SetIpeLoopbackHeaderAdjustCtl(V, bypassIpeLocalPhyPort_f, ds_data, SYS_RSV_PORT_BYPASS_IPE_ID);
    SetIpeLoopbackHeaderAdjustCtl(V, useOuterTtlMode_f, ds_data, 1);/*TMM*/
    SetIpeLoopbackHeaderAdjustCtl(V, useOuterTtlCfg_f, ds_data, 0);/*TMM*/
    cmd = DRV_IOW(IpeLoopbackHeaderAdjustCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds_data));

    field_val = 1;
    cmd = DRV_IOW(IpeE2iLoopCtl_t, IpeE2iLoopCtl_useHeaderLogicPort_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    field_val = 256;
    cmd = DRV_IOR(IpeLoopbackFieldCtl_t, DRV_ENTRY_FLAG);/*AT_TODO*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds_data));
    SetIpeLoopbackFieldCtl(V, pktTypeMapValid_f, ds_data, 1);
    SetIpeLoopbackFieldCtl(V, array_0_valid_f, ds_data, 1);
    SetIpeLoopbackFieldCtl(V, array_0_mapPacketType_f, ds_data, CTC_PARSER_PKT_TYPE_ETHERNET);
    SetIpeLoopbackFieldCtl(V, array_1_valid_f, ds_data, 1);
    SetIpeLoopbackFieldCtl(V, array_1_mapPacketType_f, ds_data, CTC_PARSER_PKT_TYPE_IP_OR_IPV6);
    SetIpeLoopbackFieldCtl(V, array_2_valid_f, ds_data, 1);
    SetIpeLoopbackFieldCtl(V, array_2_mapPacketType_f, ds_data, CTC_PARSER_PKT_TYPE_MPLS);
    SetIpeLoopbackFieldCtl(V, array_3_valid_f, ds_data, 1);
    SetIpeLoopbackFieldCtl(V, array_3_mapPacketType_f, ds_data, CTC_PARSER_PKT_TYPE_RESERVED);

    cmd = DRV_IOW(IpeLoopbackFieldCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds_data));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_ipe_route_ctl_init(uint8 lchip)
{
    uint32 cmd = 0;
    ds_t ipe_lookup_route_ctl;
    ds_t ipe_route_martian_addr;
    ds_t ipe_route_ctl;
    ParserIpChecksumCtl_m checksum_ctl;

    sal_memset(&ipe_route_ctl, 0, sizeof(ipe_route_ctl));
    cmd = DRV_IOR(IpeRouteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_route_ctl));

    SetIpeRouteCtl(V, rpfTypeForMcast_f, ipe_route_ctl, 0);
    SetIpeRouteCtl(V, exception2Discard_f, ipe_route_ctl, 0);
    SetIpeRouteCtl(V, greOption2CheckEn_f, ipe_route_ctl, 0);
    if(DRV_IS_DUET2(lchip))
    {
        SetIpeRouteCtl(V, exception3DiscardDisable_f, ipe_route_ctl, 1);
    }
    else
    {
        uint32 l3exp_discard_disable[2] = {0xFFFFFFFF, 0xFFFFFFFF};
        CTC_BIT_SET(l3exp_discard_disable[CTC_L3PDU_ACTION_INDEX_IPDA/32], CTC_L3PDU_ACTION_INDEX_IPDA%32);
        SetIpeRouteCtl(A, exception3DiscardDisable_f, ipe_route_ctl, l3exp_discard_disable);
    }

    SetIpeRouteCtl(V, exceptionSubIndex_f, ipe_route_ctl, 1);
    SetIpeRouteCtl(V, mcastEscapeToCpu_f, ipe_route_ctl, 0);
    SetIpeRouteCtl(V, mcastAddressMatchCheckDisable_f, ipe_route_ctl, 0);
    SetIpeRouteCtl(V, ipOptionsEscapeDisable_f, ipe_route_ctl, 0);
    SetIpeRouteCtl(V, routeOffsetByteShift_f, ipe_route_ctl, 0);
    SetIpeRouteCtl(V, ipTtlLimit_f, ipe_route_ctl, 2);
    SetIpeRouteCtl(V, icmpCheckRpfEn_f, ipe_route_ctl, 1);
    SetIpeRouteCtl(V, iviUseDaInfo_f, ipe_route_ctl, 1);
    SetIpeRouteCtl(V, ptIcmpEscape_f, ipe_route_ctl, 1);
    SetIpeRouteCtl(V, igmpPacketDecideMode_f, ipe_route_ctl, 1);
    SetIpeRouteCtl(V, ipBfdEscapeCtl_f, ipe_route_ctl, 1);
    SetIpeRouteCtl(V, l4CheckErrorDiscard_f, ipe_route_ctl, 7);
    SetIpeRouteCtl(V, l4CheckErrorClearException_f, ipe_route_ctl, 7);
    SetIpeRouteCtl(V, routeUseBypassIngressEdit_f, ipe_route_ctl, 1);
    SetIpeRouteCtl(V, defaultRouteIsL3DaLkpMiss_f, ipe_route_ctl, 1);
    if(DRV_FROM_AT(lchip))
    {
         SetIpeRouteCtl(V, ipDaEqualSaDiscardType_f, ipe_route_ctl, IPEDISCARDTYPE_ROUTE_ERROR_PKT_DIS);
         SetIpeRouteCtl(V, l4CheckErrorDiscardType0_f, ipe_route_ctl, IPEDISCARDTYPE_ROUTE_ERROR_PKT_DIS);
         SetIpeRouteCtl(V, l4CheckErrorDiscardType1_f, ipe_route_ctl, IPEDISCARDTYPE_ROUTE_ERROR_PKT_DIS);
         SetIpeRouteCtl(V, l4CheckErrorDiscardType2_f, ipe_route_ctl, IPEDISCARDTYPE_ROUTE_ERROR_PKT_DIS);
         SetIpeRouteCtl(V, v4McastAddrMatchDiscardType_f, ipe_route_ctl, IPEDISCARDTYPE_ROUTE_ERROR_PKT_DIS);
         SetIpeRouteCtl(V, v6McastAddrMatchDiscardType_f, ipe_route_ctl, IPEDISCARDTYPE_ROUTE_ERROR_PKT_DIS);
    }

    sal_memset(&ipe_route_martian_addr, 0, sizeof(IpeRouteMartianAddr_m));
    cmd = DRV_IOR(IpeRouteMartianAddr_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ipe_route_martian_addr));
    SetIpeRouteMartianAddr(V, flex0Mask_f, ipe_route_martian_addr, 0);
    SetIpeRouteMartianAddr(V, flex0Value_f, ipe_route_martian_addr, 0);
    SetIpeRouteMartianAddr(V, flex1Mask_f, ipe_route_martian_addr, 0);
    SetIpeRouteMartianAddr(V, flex1Value_f, ipe_route_martian_addr, 0);

    sal_memset(&ipe_lookup_route_ctl, 0, sizeof(IpeLookupRouteCtl_m));
    SetIpeLookupRouteCtl(V, martianCheckEn_f, ipe_lookup_route_ctl, 0xF);
    SetIpeLookupRouteCtl(V, martianAddressCheckDisable_f, ipe_lookup_route_ctl, 0);

    sal_memset(&checksum_ctl, 0, sizeof(checksum_ctl));
    SetParserIpChecksumCtl(V, ipChecksumCheckWithF_f, &checksum_ctl, 1);
    SetParserIpChecksumCtl(V, ipChecksumCheckWithZero_f, &checksum_ctl, 1);


    cmd = DRV_IOW(IpeRouteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_route_ctl));

    cmd = DRV_IOW(IpeLookupRouteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_lookup_route_ctl));

    cmd = DRV_IOW(IpeRouteMartianAddr_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_route_martian_addr));

    cmd = DRV_IOW(ParserIpChecksumCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &checksum_ctl));

    return CTC_E_NONE;
}


STATIC int32
_sys_usw_ipe_brg_ctl_init(uint8 lchip)
{

    int32 step = 0;
    uint8 idx = 0;
    uint32 cmd = 0;
    IpeBridgeCtl_m ipe_bridge_ctl;

    sal_memset(&ipe_bridge_ctl, 0, sizeof(IpeBridgeCtl_m));

    step = IpeBridgeCtl_array_1_protocolExceptionSubIndex_f
           - IpeBridgeCtl_array_0_protocolExceptionSubIndex_f;

    for (idx = 0; idx < 16; idx++)
    {
        DRV_SET_FIELD_V(lchip, IpeBridgeCtl_t, IpeBridgeCtl_array_0_protocolExceptionSubIndex_f + idx * step,
                        &ipe_bridge_ctl, 32);
    }

    SetIpeBridgeCtl(V, bridgeOffsetByteShift_f, &ipe_bridge_ctl, 0);
    SetIpeBridgeCtl(V, discardForceBridge_f, &ipe_bridge_ctl, 0);
    SetIpeBridgeCtl(V, macDaIsPortMacException_f, &ipe_bridge_ctl, 0);
    SetIpeBridgeCtl(V, pbbMode_f, &ipe_bridge_ctl, 0);
    SetIpeBridgeCtl(V, protocolException_f, &ipe_bridge_ctl, 0x0440);
    SetIpeBridgeCtl(V, discardForceBridge_f, &ipe_bridge_ctl, 0);
    SetIpeBridgeCtl(V, bridgeExceptionSubIndexBase_f, &ipe_bridge_ctl, 0xf);
    SetIpeBridgeCtl(V, bridgeUseBypassIngressEdit_f, &ipe_bridge_ctl, 1);
    SetIpeBridgeCtl(V, bridgeControlLayer3ExceptionEn_f, &ipe_bridge_ctl, 1);
    if (DRV_FROM_AT(lchip))
    {
        SetIpeBridgeCtl(V, macServiceIdDisable_f, &ipe_bridge_ctl, 1);
        SetIpeBridgeCtl(V, macDaDefaultEntryValidCtl_f, &ipe_bridge_ctl, 1);
    }

    cmd = DRV_IOW(IpeBridgeCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_bridge_ctl));

    return CTC_E_NONE;
}


STATIC int32
_sys_usw_ipe_fwd_ctl_init(uint8 lchip)
{
    uint32 cmd = 0;
    IpeFwdCtl_m ipe_fwd_ctl;
    IpePreLookupCtl_m pre_lkp_ctl;
    EpeHdrEditMiscCtl_m misc_ctl;

    sal_memset(&ipe_fwd_ctl, 0, sizeof(IpeFwdCtl_m));
    sal_memset(&pre_lkp_ctl, 0, sizeof(IpePreLookupCtl_m));
    sal_memset(&misc_ctl, 0, sizeof(EpeHdrEditMiscCtl_m));


    cmd = DRV_IOR(IpeFwdCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_ctl));
    SetIpeFwdCtl(V, oamDestId_f, &ipe_fwd_ctl, SYS_RSV_PORT_OAM_CPU_ID);
    SetIpeFwdCtl(V, oam_0_oamDestId_f, &ipe_fwd_ctl, SYS_RSV_PORT_OAM_CPU_ID);
    SetIpeFwdCtl(V, oam_1_oamDestId_f, &ipe_fwd_ctl, SYS_RSV_PORT_OAM_CPU1_ID);
    SetIpeFwdCtl(V, forceBackClearIngressAction_f, &ipe_fwd_ctl, 1);
    SetIpeFwdCtl(V, skipSpanPacketLoop_f, &ipe_fwd_ctl, 1);
    SetIpeFwdCtl(V, oamSdChkEn_f, &ipe_fwd_ctl, 1);
    cmd = DRV_IOW(IpeFwdCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_ctl));

    cmd = DRV_IOR(IpePreLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pre_lkp_ctl));
    SetIpePreLookupCtl(V, routerMacAllowIpmc_f, &pre_lkp_ctl, 1);
    SetIpePreLookupCtl(V, routeObeyStp_f, &pre_lkp_ctl, 1);
    SetIpePreLookupCtl(V, innerL3McastObeyFlowForceRouteCtl_f, &pre_lkp_ctl, 1);
    SetIpePreLookupCtl(V, innerL3McastObeyForceCheckCtl_f, &pre_lkp_ctl, 1);
    SetIpePreLookupCtl(V, innerL3McastObeyL3IfMcastEnCtl_f, &pre_lkp_ctl, 0);
    SetIpePreLookupCtl(V, innerL3McastObeyStpCheckCtl_f, &pre_lkp_ctl, 1);
    SetIpePreLookupCtl(V, innerL3UcastObeyFlowForceRouteCtl_f, &pre_lkp_ctl, 1);
    SetIpePreLookupCtl(V, innerL3UcastObeyForceUcastCtl_f, &pre_lkp_ctl, 1);
    SetIpePreLookupCtl(V, innerL3UcastObeyL3IfUcastEnCtl_f, &pre_lkp_ctl, 0);
    SetIpePreLookupCtl(V, innerL3UcastObeyStpCheckCtl_f, &pre_lkp_ctl, 1);
    SetIpePreLookupCtl(V, vxlanAcRouterMacUseInner_f, &pre_lkp_ctl, 1); /*AT*/
    cmd = DRV_IOW(IpePreLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pre_lkp_ctl));

    cmd = DRV_IOR(EpeHdrEditMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &misc_ctl));
    SetEpeHdrEditMiscCtl(V, cfgL3HdrLenCorrectEn_f, &misc_ctl, 0);
    SetEpeHdrEditMiscCtl(V, cfgChipIdLag_f, &misc_ctl, 0x1f);
    SetEpeHdrEditMiscCtl(V, cfgDot1AdjEn_f, &misc_ctl, 1);
    SetEpeHdrEditMiscCtl(V, cfgL4HdrEditEn_f, &misc_ctl, 1);
    SetEpeHdrEditMiscCtl(V, cfgRandSeedValueIpfixThrd_f, &misc_ctl, 0x64);
    SetEpeHdrEditMiscCtl(V, hardDiscardEn_f, &misc_ctl, 1);
    SetEpeHdrEditMiscCtl(V, hardIpfixEn_f, &misc_ctl, 1);
    SetEpeHdrEditMiscCtl(V, cfgStackAccEn_f, &misc_ctl, 1);
    SetEpeHdrEditMiscCtl(V, dataCmptEnable_f, &misc_ctl, 1);
    SetEpeHdrEditMiscCtl(V, internalIntrCheckEn_f, &misc_ctl, 1);
    SetEpeHdrEditMiscCtl(V, clearOnRead_f, &misc_ctl, 1);
    cmd = DRV_IOW(EpeHdrEditMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &misc_ctl));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_ipe_arp_ctl_init(uint8 lchip)
{
    uint32 cmd = 0;
    ds_t ds;

    sal_memset(&ds, 0, sizeof(ds_t));
    cmd = DRV_IOR(IpeIntfMapperCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeIntfMapperCtl(V, arpBroadcastRoutedPortDiscard_f,  ds, 1);
    SetIpeIntfMapperCtl(V, arpCheckExceptionEn_f,            ds, 0);
    SetIpeIntfMapperCtl(V, arpDestMacCheckEn_f,              ds, 0);
    SetIpeIntfMapperCtl(V, arpExceptionSubIndex_f,           ds, CTC_L3PDU_ACTION_INDEX_ARP);
    SetIpeIntfMapperCtl(V, arpIpCheckEn_f,                   ds, 0);
    SetIpeIntfMapperCtl(V, arpSrcMacCheckEn_f,               ds, 0);
    SetIpeIntfMapperCtl(V, arpUnicastDiscard_f,              ds, 0);
    SetIpeIntfMapperCtl(V, arpUnicastExceptionDisable_f,     ds, 1);
    SetIpeIntfMapperCtl(V, gratuitousArpExceptionEn_f,       ds, 1);/*TMM...*/
    SetIpeIntfMapperCtl(V, arpTargetIpCheckEn_f,             ds, 0);/*TMM...*/
    SetIpeIntfMapperCtl(V, gratuitousArpExceptionSubIndex_f, ds, CTC_L3PDU_ACTION_INDEX_ARP);/*TMM...*/
    SetIpeIntfMapperCtl(V, arpResponseExceptionSubIndex_f,   ds, CTC_L3PDU_ACTION_INDEX_ARP);/*TMM...*/
    cmd = DRV_IOW(IpeIntfMapperCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(&ds, 0, sizeof(ds_t));
    cmd = DRV_IOR(IpeLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeLookupCtl(V, arpExceptionSubIndex_f, ds, CTC_L3PDU_ACTION_INDEX_ARP);
    cmd = DRV_IOW(IpeLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(&ds, 0, sizeof(ds_t));
    cmd = DRV_IOR(IpePreLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpePreLookupCtl(V, arpSrcMacCheckEn_f,            ds, 0);/*TMM...*/
    SetIpePreLookupCtl(V, arpDestMacCheckEn_f,           ds, 0);/*TMM...*/
    SetIpePreLookupCtl(V, arpIpCheckEn_f,                ds, 0);/*TMM...*/
    SetIpePreLookupCtl(V, arpCheckExceptionEn_f,         ds, 0);/*TMM...*/
    SetIpePreLookupCtl(V, arpExceptionSubIndex_f,        ds, CTC_L3PDU_ACTION_INDEX_ARP);/*TMM...*/
    cmd = DRV_IOW(IpePreLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(&ds, 0, sizeof(ds_t));
    cmd = DRV_IOR(IpeBridgeCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeBridgeCtl(V, gratuitousArpExceptionEn_f,       ds, 1);/*TMM...*/
    SetIpeBridgeCtl(V, arpExceptionSubIndex_f,           ds, CTC_L3PDU_ACTION_INDEX_ARP);
    SetIpeBridgeCtl(V, gratuitousArpExceptionSubIndex_f, ds, CTC_L3PDU_ACTION_INDEX_ARP);/*TMM...*/
    SetIpeBridgeCtl(V, arpResponseExceptionSubIndex_f,   ds, CTC_L3PDU_ACTION_INDEX_ARP);/*TMM...*/
    cmd = DRV_IOW(IpeBridgeCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(&ds, 0, sizeof(ds_t));
    cmd = DRV_IOR(IpeRouteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeRouteCtl(V, interfaceClearExceptionCtl_f,       ds, 1);/*TMM...*/
    cmd = DRV_IOW(IpeRouteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));


    return CTC_E_NONE;
}

STATIC int32
_sys_usw_buffer_retrieve_ctl_init(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 tbl_id = 0;
    QWriteRsvChanCtl_m ctl;
    BufStorePktSizeChkCtl_m pkt_size;
    EpeHdrAdjustMiscCtl_m epe_ctl;
    uint32 max_len = 0;

    /* enable dma channel */
    tbl_id = QWriteRsvChanCtl_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ctl));
    SetQWriteRsvChanCtl(V,reservedChannelIdValid_f, &ctl, 1);
    SetQWriteRsvChanCtl(V,reservedChannelId_f, &ctl, MCHIP_CAP(SYS_CAP_CHANID_DROP));
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ctl));

    max_len = 16127;
    tbl_id = BufStorePktSizeChkCtl_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pkt_size));
    SetBufStorePktSizeChkCtl(V, minEopLen_f, &pkt_size, 10);
    SetBufStorePktSizeChkCtl(V, maxBufCnt_f, &pkt_size, (max_len/288));
    SetBufStorePktSizeChkCtl(V, maxEopLen_f, &pkt_size, (max_len%288));
    SetBufStorePktSizeChkCtl(V, overLenErrorChkEnable_f, &pkt_size, 1);
    SetBufStorePktSizeChkCtl(V, underLenErrorChkEnable_f, &pkt_size, 1);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    SYS_SET_TBL_ALL_DP(lchip, cmd, pkt_size);

    tbl_id = EpeHdrAdjustMiscCtl_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_ctl));
    SetEpeHdrAdjustMiscCtl(V, minPktLen_f, &epe_ctl, 10);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_ctl));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_bufferstoreCpuRxLogChannelMap_init(uint8 lchip)
{
    uint32 cmd = 0;
    BufferStoreCpuRxLogChannelMap_m cpu_rx_channel_map;

    sal_memset(&cpu_rx_channel_map,0,sizeof(BufferStoreCpuRxLogChannelMap_m));
    SetBufferStoreCpuRxLogChannelMap(V,g_0_cpuChanId_f,&cpu_rx_channel_map,0x2f);
    SetBufferStoreCpuRxLogChannelMap(V,g_1_cpuChanId_f,&cpu_rx_channel_map,0x2f);
    SetBufferStoreCpuRxLogChannelMap(V,g_2_cpuChanId_f,&cpu_rx_channel_map,0x2f);
    SetBufferStoreCpuRxLogChannelMap(V,g_3_cpuChanId_f,&cpu_rx_channel_map,0x2f);
    SetBufferStoreCpuRxLogChannelMap(V,g_4_cpuChanId_f,&cpu_rx_channel_map,MCHIP_CAP(SYS_CAP_CHANID_DMA_RX0));

    cmd = DRV_IOW(BufferStoreCpuRxLogChannelMap_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip,0,cmd,&cpu_rx_channel_map));
    return CTC_E_NONE;
}

int32 _sys_usw_ptp_ctl_init(uint8 lchip, uint8 reset)
{
    ds_t ds_master,ds_slave,ds;
    uint32 cmd = 0;
    uint32 nscnt_thrd[2]={0};
    uint32 quanta[2]={0};
    //uint16 mac_id = 0;
    uint16 index = 0;
    uint8 pp_id = 0;
    uint8 mask = 0x3F;
    uint8 mac_id = 0;
	uint32 mc_mac_valid[2] = {0};
	uint8 core_id = 0;

    sal_memset(ds, 0, sizeof(ds_t));
    #ifdef EMULATION_ENV
    cmd = DRV_IOW(CtcMacCtlReset_t, DRV_ENTRY_FLAG);
    for (index = 0; index < 20; index++)
    {
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index , cmd, &ds));
    }
    #endif
    cmd = DRV_IOW(TsRcCtl_t, DRV_ENTRY_FLAG);
    sal_memset(ds_master, 0, sizeof(ds_t));
    sal_memset(ds_slave, 0, sizeof(ds_t));
    sal_memset(ds, 0, sizeof(ds_t));

    SetTsRcCtl(V, masterMode_f, &ds_master, 1);
    SetTsRcCtl(V, loadManualMode_f, &ds_master, 1);
    SetTsRcCtl(V, captureManualMode_f, &ds_master, 1);
    SetTsRcCtl(V, useInputOnePps_f, &ds_master, 0);
    SetTsRcCtl(V, onePpsTerminate_f, &ds_master, 0);
    SetTsRcCtl(V, rcRunEn_f, &ds_master, 0);
    SetTsRcCtl(V, syncModeMask_f, &ds_master, 0);

    SetTsRcCtl(V, masterMode_f, &ds_slave,  0);
    SetTsRcCtl(V, loadManualMode_f, &ds_slave, 0);
    SetTsRcCtl(V, captureManualMode_f, &ds_slave, 0);
    SetTsRcCtl(V, onePpsCareNsCarryFlag_f, &ds_slave, 1);
    SetTsRcCtl(V, useResidualCfg_f, &ds_slave, 1);
    SetTsRcCtl(V, useInputOnePps_f, &ds_slave, 0);
    SetTsRcCtl(V, onePpsTerminate_f, &ds_slave, 0);
    SetTsRcCtl(V, rcRunEn_f, &ds_slave, 0);
    SetTsRcCtl(V, syncModeMask_f, &ds_slave, 0);
	sys_usw_port_api_get_mac_group_valid(lchip,0, &mc_mac_valid[0]);
    if (PP_NUM_PER_CORE != SYS_PP_NUM(lchip))
    {
        sys_usw_port_api_get_mac_group_valid(lchip, 1, &mc_mac_valid[1]);
    }

    for (index = 0; index < SYS_PTP_TS_RC_MAX; index++)
    {
        /*TsRcCtl init*/
        for (pp_id = 0; pp_id < SYS_PP_NUM(lchip); pp_id++)
        {
            if (pp_id == 0)
            {
                if ((index >= SYS_PTP_TS_RC_TOP && index < SYS_PTP_TS_RC_MAC) || (index==SYS_PTP_TS_RC_METER))
                {
                    (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds_master));
                }
                else
                {
					SYS_PTP_MASK_DISABLE_MAC(mc_mac_valid[0]);
					SYS_PTP_MASK_DISABLE_OAM(lchip);
                    (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds_slave));
                }
            }
            else if (pp_id == PP_NUM_PER_CORE)
            {
				SYS_PTP_MASK_DISABLE_MAC(mc_mac_valid[1]);
				SYS_PTP_MASK_DISABLE_OAM(lchip);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), index==SYS_PTP_TS_RC_METER ? &ds_master : &ds_slave));
            }
        }

    }

    for (pp_id = 0; pp_id < SYS_PP_NUM(lchip); pp_id++)
    {
        if (pp_id != 0 && pp_id != PP_NUM_PER_CORE)
        {
            continue;
        }
        for (index = 0; index < SYS_PTP_TS_RC_MAX; index++)
        {
            sal_memset(ds, 0, sizeof(ds_t));
            nscnt_thrd[1] =1;
            nscnt_thrd[0] = 0xffffffff;
            SetTsRcNsCntCarryThreshold(V, nsCntCarryThresholdLsb_f, &ds, nscnt_thrd[0]);
            SetTsRcNsCntCarryThreshold(V, nsCntCarryThresholdMsb_f, &ds, nscnt_thrd[1]);
            if (pp_id == 0)
            {
                SYS_PTP_MASK_DISABLE_MAC(mc_mac_valid[0]);
            }
            else
            {
                SYS_PTP_MASK_DISABLE_MAC(mc_mac_valid[1]);
            }
			SYS_PTP_MASK_DISABLE_OAM(lchip);
            cmd = DRV_IOW(TsRcNsCntCarryThreshold_t, DRV_ENTRY_FLAG);
            (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));

            if(!reset)
            {
                cmd = DRV_IOR(TsRcCtl_t, DRV_ENTRY_FLAG);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));
                SetTsRcCtl(V, syncModeMask_f, &ds, 0);
                cmd = DRV_IOW(TsRcCtl_t, DRV_ENTRY_FLAG);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));

                sal_memset(&ds, 0, sizeof(ds));
                cmd = DRV_IOW(TsRcQuantaDriftShadow_t, DRV_ENTRY_FLAG);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));

                cmd = DRV_IOW(TsRcSecCntShadow_t, DRV_ENTRY_FLAG);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));

                cmd = DRV_IOW(TsRcNsCntShadow_t, DRV_ENTRY_FLAG);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));

                cmd = DRV_IOW(TsRcLocalTsShadow_t, DRV_ENTRY_FLAG);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));

                cmd = DRV_IOW(TsRcDuraCntShadow_t, DRV_ENTRY_FLAG);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));

                cmd = DRV_IOW(TsRcQuantaDriftDuraShadow_t, DRV_ENTRY_FLAG);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));
            }

        }
    }

    for (pp_id = 0; pp_id < SYS_PP_NUM(lchip) && !reset; pp_id++)
    {
        if(pp_id == PP_NUM_PER_CORE) /*core 1, just set meter*/
        {
            cmd = DRV_IOR(TsRcCtl_t, DRV_ENTRY_FLAG);
            (DRV_IOCTL(lchip + pp_id, SYS_PTP_TS_RC_METER , DRV_CMD_PP_EN(cmd), &ds));
            SetTsRcCtl(V, loadManualTrigger_f, &ds, 1);
            cmd = DRV_IOW(TsRcCtl_t, DRV_ENTRY_FLAG);
            (DRV_IOCTL(lchip + pp_id, SYS_PTP_TS_RC_METER , DRV_CMD_PP_EN(cmd), &ds));
        }
        if (pp_id != 0)
        {
            continue;
        }
        for (index = 0; index < SYS_PTP_TS_RC_MAX; index++)
        {
			SYS_PTP_MASK_DISABLE_MAC(mc_mac_valid[0]);
			SYS_PTP_MASK_DISABLE_OAM(lchip);

            if (((index >= SYS_PTP_TS_RC_TOP && index < SYS_PTP_TS_RC_MAC) || (index==SYS_PTP_TS_RC_METER)))
            {
                cmd = DRV_IOR(TsRcCtl_t, DRV_ENTRY_FLAG);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));
                SetTsRcCtl(V, loadManualTrigger_f, &ds, 1);
                cmd = DRV_IOW(TsRcCtl_t, DRV_ENTRY_FLAG);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));
            }
        }
    }

    for (pp_id = 0; pp_id < SYS_PP_NUM(lchip); pp_id++)
    {
        if (pp_id != 0 && pp_id != PP_NUM_PER_CORE)
        {
            continue;
        }
        for (index = 0; index < SYS_PTP_TS_RC_MAX; index++)
        {
            if (pp_id == 0)
            {
                SYS_PTP_MASK_DISABLE_MAC(mc_mac_valid[0]);
            }
            else
            {
                SYS_PTP_MASK_DISABLE_MAC(mc_mac_valid[1]);
            }
			SYS_PTP_MASK_DISABLE_OAM(lchip);
            cmd = DRV_IOR(TsRcCtl_t, DRV_ENTRY_FLAG);
            (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));
            SetTsRcCtl(V, rcRunEn_f, &ds, 1);
            cmd = DRV_IOW(TsRcCtl_t, DRV_ENTRY_FLAG);
            (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));
        }
    }


    /*Set normal quantaDrift Shadow*/
    for (pp_id = 0; pp_id < SYS_PP_NUM(lchip); pp_id++)
    {

        if (pp_id != 0 && pp_id != PP_NUM_PER_CORE)
        {
            continue;
        }
        for (index = 0; index < SYS_PTP_TS_RC_MAX; index++)
        {
            if (pp_id == 0)
            {
                SYS_PTP_MASK_DISABLE_MAC(mc_mac_valid[0]);
            }
            else
            {
                SYS_PTP_MASK_DISABLE_MAC(mc_mac_valid[1]);
            }
			SYS_PTP_MASK_DISABLE_OAM(lchip);

            switch (sys_usw_ptp_get_rtc_id(index))
            {
                case SYS_PTP_RTC_0:
                case SYS_PTP_RTC_2 : /*ToD sec + ns + FracNs*/
                    nscnt_thrd[0] = 0xEE6B2800;
                    nscnt_thrd[1] = 0;
#ifdef EMULATION_ENV
                    quanta[1] = 3;//1.35Ghz
#else
                    quanta[1] = 4;//1Ghz
#endif
                    quanta[0] = 0;
                    break;
                case SYS_PTP_RTC_1 : /*Free Ns + FracNs*/
                    nscnt_thrd[0] = 0;
                    nscnt_thrd[1] = 1;//1Ghz
                    quanta[0] = 0;
#ifdef EMULATION_ENV
                    quanta[1] = 3;//1.35Ghz
#else
                    quanta[1] = 4;//1Ghz
#endif
                    break;
                case SYS_PTP_RTC_3 : /*NTP Sec + FracSec*/
                    nscnt_thrd[0] = 0;
                    nscnt_thrd[1] = 1;
#ifdef EMULATION_ENV
                    quanta[0] = 0x2E73FB95;
                    quanta[1] = 3;
#else
                    quanta[0] = 0x4B82FA0A;    //1Ghz
                    quanta[1] = 4;
#endif
                    break;
                case SYS_PTP_RTC_4 : /*For Ipfix, ms + ns+FracNs*/
                    nscnt_thrd[0] = 0x3D0900;
                    nscnt_thrd[1] = 0;
#ifdef EMULATION_ENV
                    quanta[1] = 3;//1.35Ghz
#else
                    quanta[1] = 4;//1Ghz
#endif
                    quanta[0] = 0;
                    break;

                case SYS_PTP_RTC_5 : /*For Meter, s + ns + FracNs*/
                    //nscnt_thrd[0] = 0xFA0;
                    nscnt_thrd[0] = 200000;
                    nscnt_thrd[1] = 0;
#ifdef EMULATION_ENV
                    quanta[1] = 3;//1.35Ghz
#else
                    quanta[1] = 4;//1Ghz
#endif
                    quanta[0] = 0;
                    break;

                default:
                    break;
            }
#ifdef EMULATION_ENV
            if (index < SYS_PTP_TS_RC_TOP)
            {
                quanta[0] = 0;
                quanta[1] = 160;//25Mhz RefClock for DMA
            }
#endif
            /*Set NsCnt Thrd*/
            sal_memset(ds, 0, sizeof(ds_t));
            SetTsRcNsCntCarryThreshold(V, nsCntCarryThresholdLsb_f, &ds, nscnt_thrd[0]);
            SetTsRcNsCntCarryThreshold(V, nsCntCarryThresholdMsb_f, &ds, nscnt_thrd[1]);

            cmd = DRV_IOW(TsRcNsCntCarryThreshold_t, DRV_ENTRY_FLAG);
            (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));

            /*Set NsCnt quanta*/
            cmd = DRV_IOR(TsRcCtl_t, DRV_ENTRY_FLAG);
            (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));
            CTC_BIT_UNSET(mask, SYS_PTP_SHADOW_DRIFT);
            SetTsRcCtl(V, syncModeMask_f, &ds, mask);
            cmd = DRV_IOW(TsRcCtl_t, DRV_ENTRY_FLAG);
            (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));

            if(!reset)
            {
                sal_memset(ds, 0, sizeof(ds_t));
                SetTsRcQuantaDriftShadow(A, quantaDriftShadow_f, &ds, quanta);
                cmd = DRV_IOW(TsRcQuantaDriftShadow_t, DRV_ENTRY_FLAG);/* syncModeMask[SYS_PTP_SHADOW_DRIFT]should be clean*/
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));
            }
        }
        sal_memset(ds, 0, sizeof(ds_t));
        SetTsEngineTsSelection(V, syncIntf0TsSel_f, &ds, 0);/*RTC0*/
        SetTsEngineTsSelection(V, syncIntf1TsSel_f, &ds, 1);/*RTC2*/
        cmd = DRV_IOW(TsEngineTsSelection_t, DRV_ENTRY_FLAG);
        (DRV_IOCTL(lchip + pp_id, 0 , DRV_CMD_PP_EN(cmd), &ds));

    }

    for (pp_id = 0; pp_id < SYS_PP_NUM(lchip); pp_id++)
    {
        if(pp_id == PP_NUM_PER_CORE) /*core 1, just set meter*/
        {
            cmd = DRV_IOR(TsRcCtl_t, DRV_ENTRY_FLAG);
            (DRV_IOCTL(lchip + pp_id, SYS_PTP_TS_RC_METER , DRV_CMD_PP_EN(cmd), &ds));
            SetTsRcCtl(V, loadManualTrigger_f, &ds, 1);
            cmd = DRV_IOW(TsRcCtl_t, DRV_ENTRY_FLAG);
            (DRV_IOCTL(lchip + pp_id, SYS_PTP_TS_RC_METER , DRV_CMD_PP_EN(cmd), &ds));
        }
        if (pp_id != 0)
        {
            continue;
        }
        for (index = 0; index < SYS_PTP_TS_RC_MAX; index++)
        {
			SYS_PTP_MASK_DISABLE_MAC(mc_mac_valid[0]);
			SYS_PTP_MASK_DISABLE_OAM(lchip);

            if (((index >= SYS_PTP_TS_RC_TOP && index < SYS_PTP_TS_RC_MAC) || (index==SYS_PTP_TS_RC_METER)))
            {
                cmd = DRV_IOR(TsRcCtl_t, DRV_ENTRY_FLAG);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));
                SetTsRcCtl(V, loadManualTrigger_f, &ds, 1);
                cmd = DRV_IOW(TsRcCtl_t, DRV_ENTRY_FLAG);
                (DRV_IOCTL(lchip + pp_id, index , DRV_CMD_PP_EN(cmd), &ds));
            }
        }
    }
    for (core_id = 0; core_id < 2; core_id++)
    {
        for (mac_id = 0; mac_id < MCHIP_CAP(SYS_CAP_MAC_NUM_PER_CORE); mac_id++)
        {
            if (!((1 << (mac_id/MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM))) & mc_mac_valid[core_id]))
            {
                continue;
            }
            cmd = DRV_IOR(McHataRxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, mac_id / MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM), DRV_CMD_PP_EN(cmd), &ds));
            SetMcHataRxCfg(V, cfgHataRxFreeRtcId0_f + mac_id % MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM), &ds, MCHIP_CAP(SYS_CAP_PTP_FREE_RTC_ID));
            cmd = DRV_IOW(McHataRxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, mac_id / MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM), DRV_CMD_PP_EN(cmd), &ds));

            cmd = DRV_IOR(McHataTxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, mac_id / MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM), DRV_CMD_PP_EN(cmd), &ds));
            SetMcHataTxCfg(V, cfgHataTxFreeRtcId0_f + mac_id % MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM), &ds, MCHIP_CAP(SYS_CAP_PTP_FREE_RTC_ID));
            cmd = DRV_IOW(McHataTxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, mac_id / MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM), DRV_CMD_PP_EN(cmd), &ds));
        }
    }

    for(index = 0; index < MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP); index++)
    {
        /*IPE/EPE*/
        cmd = DRV_IOR(DsSrcChannel_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds));
        SetDsSrcChannel(V,freeRtcId_f, &ds, 1);
        SetDsSrcChannel(V,todRtcId_f,&ds,0);
        SetDsSrcChannel(V,macSelectTsFormat_f,&ds,1);
        cmd = DRV_IOW(DsSrcChannel_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds));
        
        cmd = DRV_IOR(DsDestChannel_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds));
        SetDsDestChannel(V,ntpRtcId_f,&ds,3);
        SetDsDestChannel(V,freeRtcId_f, &ds, 1);
        SetDsDestChannel(V,todRtcId_f,&ds,0);
        SetDsDestChannel(V,ptpTcIngressTsFormat_f,&ds,1);
        SetDsDestChannel(V,ptpCpuIngressTsFormat_f,&ds,1);
        cmd = DRV_IOW(DsDestChannel_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds));
    }

    
    for (core_id = 0; core_id < 2; core_id++)
    {
        for (index = 0; index < 20; index++)
        {
            if (!((1 << index) & mc_mac_valid[core_id]))
            {
                continue;
            }
            /*McMac*/
            cmd = DRV_IOR(McMacMacRxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_PP_EN(cmd), &ds));
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_0_cfgMcMacRxSelTsFormat_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_1_cfgMcMacRxSelTsFormat_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_2_cfgMcMacRxSelTsFormat_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_3_cfgMcMacRxSelTsFormat_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_4_cfgMcMacRxSelTsFormat_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_5_cfgMcMacRxSelTsFormat_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_6_cfgMcMacRxSelTsFormat_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_7_cfgMcMacRxSelTsFormat_f, &ds, 1);

            SetMcMacMacRxCfg(V, cfgMcMacMacRx_0_cfgMcMacRxFreeRtcId_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_1_cfgMcMacRxFreeRtcId_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_2_cfgMcMacRxFreeRtcId_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_3_cfgMcMacRxFreeRtcId_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_4_cfgMcMacRxFreeRtcId_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_5_cfgMcMacRxFreeRtcId_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_6_cfgMcMacRxFreeRtcId_f, &ds, 1);
            SetMcMacMacRxCfg(V, cfgMcMacMacRx_7_cfgMcMacRxFreeRtcId_f, &ds, 1);

            cmd = DRV_IOW(McMacMacRxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_PP_EN(cmd), &ds));

            cmd = DRV_IOR(McMacMacTxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_PP_EN(cmd), &ds));
            SetMcMacMacTxCfg(V, cfgMcMacMacTx_0_cfgMcMacTxFreeRtcId_f, &ds, 1);
            SetMcMacMacTxCfg(V, cfgMcMacMacTx_1_cfgMcMacTxFreeRtcId_f, &ds, 1);
            SetMcMacMacTxCfg(V, cfgMcMacMacTx_2_cfgMcMacTxFreeRtcId_f, &ds, 1);
            SetMcMacMacTxCfg(V, cfgMcMacMacTx_3_cfgMcMacTxFreeRtcId_f, &ds, 1);
            SetMcMacMacTxCfg(V, cfgMcMacMacTx_4_cfgMcMacTxFreeRtcId_f, &ds, 1);
            SetMcMacMacTxCfg(V, cfgMcMacMacTx_5_cfgMcMacTxFreeRtcId_f, &ds, 1);
            SetMcMacMacTxCfg(V, cfgMcMacMacTx_6_cfgMcMacTxFreeRtcId_f, &ds, 1);
            SetMcMacMacTxCfg(V, cfgMcMacMacTx_7_cfgMcMacTxFreeRtcId_f, &ds, 1);

            cmd = DRV_IOW(McMacMacTxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_PP_EN(cmd), &ds));

            /*HataRx/HataTx*/
            cmd = DRV_IOR(McHataRxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_PP_EN(cmd), &ds));
            SetMcHataRxCfg(V, cfgHataRxSelTsFormat_f, &ds, 0xFF);
            cmd = DRV_IOW(McHataRxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_PP_EN(cmd), &ds));
        
            cmd = DRV_IOR(McHataTxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_PP_EN(cmd), &ds));
            SetMcHataTxCfg(V, cfgHataTxSelTsFormat_f, &ds, 0xFF);
            cmd = DRV_IOW(McHataTxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_PP_EN(cmd), &ds));

            cmd = DRV_IOR(McHataTxFifoThrd_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_PP_EN(cmd), &ds));
            SetMcHataTxFifoThrd(V, cfgHataTxTsToCpuFifoAFullThrd_f, &ds, 0x3f);
            cmd = DRV_IOW(McHataTxFifoThrd_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_PP_EN(cmd), &ds));
        }
    }
	return CTC_E_NONE;

}


int32
sys_usw_ptp_reset_hw(uint8 lchip, void* p_user_data)
{
    CTC_ERROR_RETURN(_sys_usw_ptp_ctl_init(lchip, 1));
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_qmgr_ctl_init(uint8 lchip)
{
    uint32 cmd = 0;
    QWritePktLenCtl_m  length_adjust;
    LagEngineCtl_m lag_engine_ctl;
    sal_memset(&length_adjust, 0, sizeof(QWritePktLenCtl_m));

    cmd = DRV_IOR(QWritePktLenCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &length_adjust));

    SetQWritePktLenCtl(V, g0_0_packetLengthAdjustType_f , &length_adjust, 0);
    SetQWritePktLenCtl(V, g0_0_packetLengthAdjust_f , &length_adjust, 0);
    SetQWritePktLenCtl(V, g0_1_packetLengthAdjustType_f , &length_adjust, 0);
    SetQWritePktLenCtl(V, g0_1_packetLengthAdjust_f , &length_adjust, 4);
    SetQWritePktLenCtl(V, g0_2_packetLengthAdjustType_f , &length_adjust, 0);
    SetQWritePktLenCtl(V, g0_2_packetLengthAdjust_f , &length_adjust, 8);
    SetQWritePktLenCtl(V, g0_3_packetLengthAdjustType_f , &length_adjust, 0);
    SetQWritePktLenCtl(V, g0_3_packetLengthAdjust_f , &length_adjust, 12);
    SetQWritePktLenCtl(V, g0_4_packetLengthAdjustType_f , &length_adjust, 0);
    SetQWritePktLenCtl(V, g0_4_packetLengthAdjust_f , &length_adjust, 14);
    SetQWritePktLenCtl(V, g0_5_packetLengthAdjustType_f , &length_adjust, 0);
    SetQWritePktLenCtl(V, g0_5_packetLengthAdjust_f , &length_adjust, 16);
    SetQWritePktLenCtl(V, g0_6_packetLengthAdjustType_f , &length_adjust, 0);
    SetQWritePktLenCtl(V, g0_6_packetLengthAdjust_f , &length_adjust, 18);
    SetQWritePktLenCtl(V, g0_7_packetLengthAdjustType_f , &length_adjust, 0);
    SetQWritePktLenCtl(V, g0_7_packetLengthAdjust_f , &length_adjust, 22);

    cmd = DRV_IOW(QWritePktLenCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &length_adjust));

    /*Lag Engine Ctl init*/
    sal_memset(&lag_engine_ctl, 0, sizeof(LagEngineCtl_m));
    cmd = DRV_IOR(LagEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lag_engine_ctl));
    SetLagEngineCtl(V, sgmacEn_f, &lag_engine_ctl, 1);
    SetLagEngineCtl(V, discardUnkownSgmacGroup_f, &lag_engine_ctl, 1);
    cmd = DRV_IOW(LagEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lag_engine_ctl));
    return CTC_E_NONE;

}

int32
sys_usw_lkup_adjust_len_index(uint8 lchip, uint8 adjust_len, uint8* len_index)
{
    uint32 cmd;
    uint8 index = 0;
    uint32 length = 0;
    uint8 bfind = 0;
    uint8 step = 0;

    SYS_REGISTER_INIT_CHECK;

    step = QWritePktLenCtl_g0_1_packetLengthAdjust_f - QWritePktLenCtl_g0_0_packetLengthAdjust_f;
    for (index = 0; index < 8; index++)
    {
        cmd = DRV_IOR(QWritePktLenCtl_t, QWritePktLenCtl_g0_0_packetLengthAdjust_f + index*step);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &length));

        if (length >= adjust_len)
        {
            *len_index = index;
            bfind = 1;
            break;
        }
    }
	if(!bfind)
	{
	   *len_index  = 7;
	}

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_ipg_init(uint8 lchip)
{
    uint32 cmd = 0;
    IpeIpgCtl_m  ipe_ipg_ctl;
    EpeIpgCtl_m  epe_ipg_ctl;

    sal_memset(&ipe_ipg_ctl, 0, sizeof(ipe_ipg_ctl));
    sal_memset(&epe_ipg_ctl, 0, sizeof(epe_ipg_ctl));

    SetIpeIpgCtl(V, array_0_ipg_f, &ipe_ipg_ctl, 20);
    SetIpeIpgCtl(V, array_1_ipg_f, &ipe_ipg_ctl, 20);
    SetIpeIpgCtl(V, array_2_ipg_f, &ipe_ipg_ctl, 20);
    SetIpeIpgCtl(V, array_3_ipg_f, &ipe_ipg_ctl, 20);

    SetEpeIpgCtl(V, array_0_ipg_f, &epe_ipg_ctl, 20);
    SetEpeIpgCtl(V, array_1_ipg_f, &epe_ipg_ctl, 20);
    SetEpeIpgCtl(V, array_2_ipg_f, &epe_ipg_ctl, 20);
    SetEpeIpgCtl(V, array_3_ipg_f, &epe_ipg_ctl, 20);

    cmd = DRV_IOW(IpeIpgCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_ipg_ctl));

    cmd = DRV_IOW(EpeIpgCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_ipg_ctl));

    return CTC_E_NONE;

}

int32
sys_usw_register_chip_init(uint8 lchip)
{
    IpeFwdCtl_m      ipe_fwd_ctl;
    EpePktProcCtl_m EpePktProcCtl;
    uint32 cmd = 0;
    uint8 mtu_ck_sel = 0;
    uint8 cut_through_en = p_usw_chip_master[lchip]->cut_through_en;
    uint8 index = 0;
    MapMsgDestMap_m map_msg;
    uint32 field_val = 0;

    cmd = DRV_IOR(EpePktProcCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &EpePktProcCtl));
    if (DRV_FROM_TMM(lchip))
    {
        mtu_ck_sel = (cut_through_en == 0) ? (0x03 | 0x04) :  (0x03 | 0x00) ;
        SetEpePktProcCtl(V, mtuCheckSelectBits_f, &EpePktProcCtl, mtu_ck_sel);
        SetEpePktProcCtl(V, mtuCheckSelectBits0_f, &EpePktProcCtl, mtu_ck_sel);
    }
    else
    {
        if (cut_through_en == 0)
        {
            if (DRV_IS_DUET2(lchip))
            {
                field_val = 0;
                cmd = DRV_IOW(QMgrEnqReserved_t, QMgrEnqReserved_reserved_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            }
            SetEpePktProcCtl(V, mtuCheckSelectBits_f, &EpePktProcCtl, 0x06);
        }
        else
        {
            if (DRV_IS_DUET2(lchip))
            {
                field_val = 0xf;
                cmd = DRV_IOW(QMgrEnqReserved_t, QMgrEnqReserved_reserved_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            }
            SetEpePktProcCtl(V, mtuCheckSelectBits_f, &EpePktProcCtl, 0x03);
        }
    }
    cmd = DRV_IOW(EpePktProcCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &EpePktProcCtl));

    sal_memset(&ipe_fwd_ctl, 0, sizeof(ipe_fwd_ctl));
    cmd = DRV_IOR(IpeFwdCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_ctl));
    SetIpeFwdCtl(V, cutThroughEn_f, &ipe_fwd_ctl, cut_through_en);
    SetIpeFwdCtl(V, cutThroughDontCareException_f, &ipe_fwd_ctl, cut_through_en);
    cmd = DRV_IOW(IpeFwdCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_ctl));

    for (index = 0; index < SYS_DMA_INFO_MAX_SUB_TYPE && (DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)); index++)
    {
        sal_memset(&map_msg, 0, sizeof(MapMsgDestMap_m));
        /* firstly  read */
        cmd = DRV_IOR(MapMsgDestMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &map_msg));
        field_val = GetMapMsgDestMap(V, mapBmp_f, &map_msg);

        /* secondly  set */
        field_val = field_val | 0x1;
        SetMapMsgDestMap(V, mapBmp_f, &map_msg, field_val);
        if (index <= 31)
        {
            field_val = 2;/* ipfix */
        }
        else if (index >= 32 && index <= 37)
        {
            field_val = 3;/* buffer monitor */
        }
        else if (index == 38 || index == 39)
        {
            field_val = 4;/* Latency monitor */
        }
        else if (index == 40 || index == 41)
        {
            field_val = 5;/* EFD/DLB monitor */
        }
        else if (index == 42)
        {
            field_val = 6;/* twamp stats info */
        }
        else if (index == 43 || index == 44)
        {
            field_val = 7;/* sc oam master info */
        }
        else if (index == 45 || index == 46)
        {
            field_val = 0;/* learning aging */
        }
        else if (index == 47)
        {
            field_val = 1;/* hash dump */
        }
        SetMapMsgDestMap(V, dmaChan_f, &map_msg, field_val);

        /* finally write */
        cmd = DRV_IOW(MapMsgDestMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &map_msg));
    }

    return CTC_E_NONE;
}


int32
_sys_usw_set_glb_scl_property(uint8 lchip, ctc_global_scl_property_t* pscl_property)
{
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint32 fld_id_mode[4] = {0,0,UserIdTcamCtl_array_0_v6BasicKeyIpAddressMode_f, UserIdTcamCtl_array_1_v6BasicKeyIpAddressMode_f};
    uint32 fld_id_da_mode[4] = {0,0,UserIdTcamCtl_array_0_v6BasicKeyMode0IpAddr1Encode_f, UserIdTcamCtl_array_1_v6BasicKeyMode0IpAddr1Encode_f};
    uint32 fld_id_sa_mode[4] = {0,0,UserIdTcamCtl_array_0_v6BasicKeyMode0IpAddr2Encode_f, UserIdTcamCtl_array_1_v6BasicKeyMode0IpAddr2Encode_f};
    CTC_PTR_VALID_CHECK(pscl_property);
    CTC_MAX_VALUE_CHECK(pscl_property->lkup_level, 3);

    if ((pscl_property->lkup_level >= 2) && (pscl_property->lkup_level <= 3))
    {
        if ((pscl_property->ipv6_single_mode > 2)
            || (pscl_property->key_ipv6_da_addr_mode >= CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_MAX)
            || (pscl_property->key_ipv6_sa_addr_mode >= CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_MAX))
        {
            return CTC_E_INVALID_PARAM;
        }

        field_val = pscl_property->ipv6_single_mode;
        cmd = DRV_IOW(UserIdTcamCtl_t, fld_id_mode[pscl_property->lkup_level]);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        field_val = pscl_property->key_ipv6_da_addr_mode;
        cmd = DRV_IOW(UserIdTcamCtl_t, fld_id_da_mode[pscl_property->lkup_level]);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        field_val = pscl_property->key_ipv6_sa_addr_mode;
        cmd = DRV_IOW(UserIdTcamCtl_t, fld_id_sa_mode[pscl_property->lkup_level]);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    }
    else if (pscl_property->lkup_level <= 1)
    {
        uint32 mask[4] = {0};
        uint32 ipv6_da_mask_short[2] = {UserIdCtl_g_0_sr6WildcardShort_f, UserIdCtl_g_1_sr6WildcardShort_f};
        uint32 ipv6_da_mask[2] = {UserIdCtl_g_0_sr6Wildcard_f, UserIdCtl_g_1_sr6Wildcard_f};

        CTC_MAX_VALUE_CHECK(pscl_property->key_ipv6_da_addr_len, 128);

        IPV6_LEN_TO_MASK(mask, pscl_property->key_ipv6_da_addr_len);

        mask[0] = ~mask[0];
        mask[1] = ~mask[1];
        mask[2] = ~mask[2];
        mask[3] = ~mask[3];

        cmd = DRV_IOW(UserIdCtl_t, ipv6_da_mask[pscl_property->lkup_level]);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, mask));

        field_val = mask[3];
        cmd = DRV_IOW(UserIdCtl_t, ipv6_da_mask_short[pscl_property->lkup_level]);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        field_val = 0x6;
        cmd = DRV_IOW(UserIdCtl_t, UserIdCtl_sr6Mode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        cmd = DRV_IOR(UserIdCtl_t, UserIdCtl_sr6ForceIpv4_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        if (pscl_property->key_ipv6_da_addr_len <= 32)
        {
            CTC_BIT_SET(field_val, pscl_property->lkup_level);
            cmd = DRV_IOW(UserIdCtl_t, UserIdCtl_sr6ForceIpv4_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        else
        {
            CTC_BIT_UNSET(field_val, pscl_property->lkup_level);
            cmd = DRV_IOW(UserIdCtl_t, UserIdCtl_sr6ForceIpv4_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
#if (FEATURE_MODE == 0)
        CTC_ERROR_RETURN(sys_usw_srv6_set_global_cfg(lchip, NULL, pscl_property->key_ipv6_da_addr_len, pscl_property->lkup_level));
#endif
    }

    return CTC_E_NONE;
}

int32
_sys_usw_get_glb_scl_property(uint8 lchip, ctc_global_scl_property_t* pscl_property)
{
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint32 tbl_id = DRV_FROM_TMM(lchip) ? UserIdTcamCtl_t : IpeUserIdTcamCtl_t;
    uint32 fld_id_mode[4] = {IpeUserIdTcamCtl_array_0_v6BasicKeyIpAddressMode_f,
        IpeUserIdTcamCtl_array_1_v6BasicKeyIpAddressMode_f,IpeUserIdTcamCtl_array_2_v6BasicKeyIpAddressMode_f, IpeUserIdTcamCtl_array_3_v6BasicKeyIpAddressMode_f};
    uint32 fld_id_da_mode[4] = {IpeUserIdTcamCtl_array_0_v6BasicKeyMode0IpAddr1Encode_f,IpeUserIdTcamCtl_array_1_v6BasicKeyMode0IpAddr1Encode_f,
        IpeUserIdTcamCtl_array_2_v6BasicKeyMode0IpAddr1Encode_f, IpeUserIdTcamCtl_array_3_v6BasicKeyMode0IpAddr1Encode_f};
    uint32 fld_id_sa_mode[4] = {IpeUserIdTcamCtl_array_0_v6BasicKeyMode0IpAddr2Encode_f,IpeUserIdTcamCtl_array_1_v6BasicKeyMode0IpAddr2Encode_f,
        IpeUserIdTcamCtl_array_2_v6BasicKeyMode0IpAddr2Encode_f, IpeUserIdTcamCtl_array_3_v6BasicKeyMode0IpAddr2Encode_f};
    CTC_PTR_VALID_CHECK(pscl_property);
    CTC_MAX_VALUE_CHECK(pscl_property->lkup_level, 3);

    if(DRV_FROM_TMM(lchip))
    {
        fld_id_mode[2] = UserIdTcamCtl_array_0_v6BasicKeyIpAddressMode_f;
        fld_id_mode[3] = UserIdTcamCtl_array_1_v6BasicKeyIpAddressMode_f;
        fld_id_da_mode[2] = UserIdTcamCtl_array_0_v6BasicKeyMode0IpAddr1Encode_f;
        fld_id_da_mode[3] = UserIdTcamCtl_array_1_v6BasicKeyMode0IpAddr1Encode_f;
        fld_id_sa_mode[2] = UserIdTcamCtl_array_0_v6BasicKeyMode0IpAddr2Encode_f;
        fld_id_sa_mode[3] = UserIdTcamCtl_array_1_v6BasicKeyMode0IpAddr2Encode_f;

        if (pscl_property->lkup_level < 2)
        {
            uint32 mask[4] = {0};
            ds1_t ds;

            cmd = DRV_IOR(UserIdCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

            if (1 == pscl_property->lkup_level)
            {
                GetUserIdCtl(A, g_1_sr6Wildcard_f, ds, mask);
            }
            else
            {
                GetUserIdCtl(A, g_0_sr6Wildcard_f, ds, mask);
            }

            mask[0] = ~mask[0];
            mask[1] = ~mask[1];
            mask[2] = ~mask[2];
            mask[3] = ~mask[3];

            IPV6_MASK_TO_LEN(mask, pscl_property->key_ipv6_da_addr_len);
            return CTC_E_NONE;
        }
    }

    cmd = DRV_IOR(tbl_id, fld_id_mode[pscl_property->lkup_level]);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    pscl_property->ipv6_single_mode = field_val;

    cmd = DRV_IOR(tbl_id, fld_id_da_mode[pscl_property->lkup_level]);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    pscl_property->key_ipv6_da_addr_mode = (field_val > CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_16)? CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_16 : field_val;

    cmd = DRV_IOR(tbl_id, fld_id_sa_mode[pscl_property->lkup_level]);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    pscl_property->key_ipv6_sa_addr_mode = (field_val > CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_16)? CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_16 : field_val;

    return CTC_E_NONE;
}

#define epe_acl_ctl     ipe_fwd_acl

int32
_sys_usw_set_glb_acl_property(uint8 lchip, ctc_global_acl_property_t* pacl_property, uint8 inner)
{
    uint32 cmd = 0;
    uint32 value = 0;
    uint8  step = 0;
    uint8 loop = 0;
    uint8 fwd_ext_key_u1_bmp = 0;
    uint8  key_cid_valid = 0;
    uint8 block_base = 0;
    FlowTcamLookupCtl_m  flow_ctl;
    ds1_t                ipe_fwd_acl;
    EpePktProcCtl_m      epe_pkt_proc_ctl;

    cmd = DRV_IOR(FlowTcamLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &flow_ctl));

    if ( DRV_FROM_TMM(lchip) && pacl_property->dir == CTC_INGRESS)
    {
        uint32 field_val = 0;
        uint8 step = IpeCflexAclCtl_cflexAcllkpLevel_1_cflexAclEnable_f - IpeCflexAclCtl_cflexAcllkpLevel_0_cflexAclEnable_f;
        IpeCflexAclCtl_m IpeCflexctl;

        CTC_MAX_VALUE_CHECK(pacl_property->lkup_level,MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM)-1);

        field_val = pacl_property->stk_hdr_lkup_en?1:0;

        cmd = DRV_IOR(IpeCflexAclCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &IpeCflexctl));

        SetIpeCflexAclCtl(V, cflexAcllkpLevel_0_cflexAclEnable_f + pacl_property->lkup_level*step, &IpeCflexctl, field_val);
        SetIpeCflexAclCtl(V, cflexAcllkpLevel_0_cflexLookupAclEnable_f + pacl_property->lkup_level*step, &IpeCflexctl, field_val);


        cmd = DRV_IOW(IpeCflexAclCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &IpeCflexctl));
    }
    if (DRV_FROM_TMM(lchip) && !inner)
    {
        if (pacl_property->dir == CTC_INGRESS || pacl_property->dir == CTC_BOTH_DIRECTION)
        {
            CTC_ERROR_RETURN(sys_usw_acl_set_action_priority(lchip, pacl_property->lkup_level, pacl_property->action_pri));
        }
        if (pacl_property->dir == CTC_EGRESS || pacl_property->dir == CTC_BOTH_DIRECTION)
        {
            block_base = MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM);
            CTC_ERROR_RETURN(sys_usw_acl_set_action_priority(lchip, pacl_property->lkup_level+block_base, pacl_property->action_pri));
        }
    }

    if(pacl_property->dir == CTC_INGRESS || pacl_property->dir == CTC_BOTH_DIRECTION )
    {
        IpePreLookupAclCtl_m ipe_acl_ctl;
        IpeAclQosCtl_m       ipe_aclqos_ctl;

        CTC_MAX_VALUE_CHECK(pacl_property->lkup_level, MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM)-1);

        if (!DRV_FROM_TMM(lchip))
        {
            CTC_MAX_VALUE_CHECK(pacl_property->random_log_pri, 7);
        }

        /*AT*/
        cmd = DRV_IOR(IpeFwdAclCtl2_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
        SetIpeFwdAclCtl2(V, gLookup_0_dropPktDisableAcl_f+pacl_property->lkup_level, &ipe_fwd_acl, pacl_property->discard_pkt_lkup_en? 0: 3);
        cmd = DRV_IOW(IpeFwdAclCtl2_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));

        /*discard_pkt_lkup_en*/
        cmd = DRV_IOR(IpeFwdAclCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
        value = GetIpeFwdAclCtl(V, dropPktDisableAcl_f, &ipe_fwd_acl);
        if (!pacl_property->discard_pkt_lkup_en)
        {
            CTC_BIT_SET(value , pacl_property->lkup_level);
        }
        else
        {
            CTC_BIT_UNSET(value , pacl_property->lkup_level);
        }
        SetIpeFwdAclCtl(V, dropPktDisableAcl_f, &ipe_fwd_acl, value);
        DRV_SET_FLD_V2(lchip, IpeFwdAclCtl_t, "gLookup_0_dropPktDisableAcl", &ipe_fwd_acl, pacl_property->discard_pkt_lkup_en? 0: 3, "_0_", pacl_property->lkup_level);
        for (loop = 0; loop < MAX_CTC_PARSER_L3_TYPE; loop++ )
        {
            if (pacl_property->copp_key_use_ext_mode[loop])
            {
                CTC_BIT_SET(value, loop);
            }
            else
            {
                CTC_BIT_UNSET(value, loop);
            }
        }
        SetIpeFwdAclCtl(V, useCopp640bitsKey_f, &ipe_fwd_acl, value);
        SetIpeFwdAclCtl(V, useCoppExtKey_f, &ipe_fwd_acl, value);

        for (loop = 0; loop < MAX_CTC_PARSER_L3_TYPE; loop++ )
        {
            if (pacl_property->l2l3_ext_key_use_l2l3_key[loop])
            {
                CTC_BIT_SET(value, loop);
            }
            else
            {
                CTC_BIT_UNSET(value, loop);
            }
        }
        SetIpeFwdAclCtl(V, aclForceL2L3ExtKeyToL2L3Key_f, &ipe_fwd_acl, value);
        SetIpeFwdAclCtl(V, aclForceL3BasicV6ToL3ExtV6_f, &ipe_fwd_acl, pacl_property->l3_key_ipv6_use_compress_addr?0:1);

        if ((SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) && DRV_IS_TSINGMA(lchip))
        {
            /*fid action config*/
            cmd = DRV_IOR(IpeAclReserved_t, IpeAclReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if(pacl_property->action_fid_en)
            {
                CTC_BIT_SET(value, pacl_property->lkup_level);
            }
            else
            {
                CTC_BIT_UNSET(value, pacl_property->lkup_level);
            }
            cmd = DRV_IOW(IpeAclReserved_t, IpeAclReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        }

        if (DRV_FROM_TMM(lchip))
        {
            SetIpeFwdAclCtl(V, bridgePktAclObeyStpBlock_f, &ipe_fwd_acl, (pacl_property->stp_blocked_pkt_lkup_en)?0:1);
            SetIpeFwdAclCtl(V, nonBridgePktAclObeyStpBlock_f, &ipe_fwd_acl, (pacl_property->stp_blocked_pkt_lkup_en)?0:1);
        }
        else
        {
              cmd = DRV_IOR(IpePreLookupAclCtl_t, DRV_ENTRY_FLAG);
              CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_acl_ctl));
              SetIpePreLookupAclCtl(V, bridgePktAclObeyStpBlock_f, &ipe_acl_ctl, (pacl_property->stp_blocked_pkt_lkup_en)?0:1);
              SetIpePreLookupAclCtl(V, nonBridgePktAclObeyStpBlock_f, &ipe_acl_ctl, (pacl_property->stp_blocked_pkt_lkup_en)?0:1);
              SetIpePreLookupAclCtl(V, layer2TypeUsedAsVlanNum_f, &ipe_acl_ctl, (pacl_property->l2_type_as_vlan_num)?1:0);
              cmd = DRV_IOW(IpePreLookupAclCtl_t, DRV_ENTRY_FLAG);
              CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_acl_ctl));

              /*v6 basic key*/
            step = FlowTcamLookupCtl_gIngrAcl_1_v6BasicKeyMode0IpAddr1Encode_f -
                    FlowTcamLookupCtl_gIngrAcl_0_v6BasicKeyMode0IpAddr1Encode_f;
            SetFlowTcamLookupCtl(V, gIngrAcl_0_v6BasicKeyMode0IpAddr1Encode_f + pacl_property->lkup_level *step,
                                      &flow_ctl, pacl_property->key_ipv6_da_addr_mode);
            SetFlowTcamLookupCtl(V, gIngrAcl_0_v6BasicKeyMode0IpAddr2Encode_f + pacl_property->lkup_level *step,
                                      &flow_ctl, pacl_property->key_ipv6_sa_addr_mode);

            /*fwd basic key*/
            step = FlowTcamLookupCtl_gIngrAcl_1_v6ForwardBasicKeyMode0IpAddr1Encode_f -
                    FlowTcamLookupCtl_gIngrAcl_0_v6ForwardBasicKeyMode0IpAddr1Encode_f;
            SetFlowTcamLookupCtl(V, gIngrAcl_0_v6ForwardBasicKeyMode0IpAddr1Encode_f + pacl_property->lkup_level *step,
                                      &flow_ctl, pacl_property->key_ipv6_da_addr_mode);
            SetFlowTcamLookupCtl(V, gIngrAcl_0_v6ForwardBasicKeyMode0IpAddr2Encode_f + pacl_property->lkup_level *step,
                                      &flow_ctl, pacl_property->key_ipv6_sa_addr_mode);
             /*cid key*/
            SetFlowTcamLookupCtl(V, ingrSgaclKeyIpv6DaAddrEncode_f,&flow_ctl, pacl_property->cid_key_ipv6_da_addr_mode);
            SetFlowTcamLookupCtl(V, ingrSgaclKeyIpv6SaAddrEncode_f,&flow_ctl, pacl_property->cid_key_ipv6_sa_addr_mode);

            /*CID enable*/
            step = FlowTcamLookupCtl_gIngrAcl_1_categoryIdFieldValid_f -
                    FlowTcamLookupCtl_gIngrAcl_0_categoryIdFieldValid_f;
            SetFlowTcamLookupCtl(V, gIngrAcl_0_categoryIdFieldValid_f + pacl_property->lkup_level *step,
                                      &flow_ctl, pacl_property->key_cid_en);
            /*Copp use udf*/
            SetFlowTcamLookupCtl(V, coppBasicKeyUseUdfShareType_f,&flow_ctl, pacl_property->copp_key_use_udf ? 0xFFFF : 0);
            SetFlowTcamLookupCtl(V, coppExtKeyUdfShareType_f,&flow_ctl, pacl_property->copp_ext_key_use_udf? 0 : 0xFFFF);

            /*random log priority*/
            if (!DRV_FROM_TMM(lchip))
            {
                step = IpeAclQosCtl_aclLogSelectMap_1_logBlockNum_f - IpeAclQosCtl_aclLogSelectMap_0_logBlockNum_f;
                cmd = DRV_IOR(IpeAclQosCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_aclqos_ctl));
                SetIpeAclQosCtl(V, aclLogSelectMap_0_logBlockNum_f+step*pacl_property->lkup_level, &ipe_aclqos_ctl, pacl_property->random_log_pri);
                cmd = DRV_IOW(IpeAclQosCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_aclqos_ctl));
            }
        }

        cmd = DRV_IOW(IpeFwdAclCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));

        /* mpls im per level en */
        if (MCHIP_ACL(lchip)->set_league_global_config)
        {
            uint8 pp_id = 0;
            sys_acl_league_glb_config_t config;
            sal_memset(&config, 0, sizeof(sys_acl_league_glb_config_t));\
            config.block_id = pacl_property->lkup_level;
            config.npm_im_en = pacl_property->npm_im_en? 1: 0;
            config.op_type = SYS_ACL_LEAGUE_CONFIG_NPM_IM;
            for(pp_id = 0; pp_id < SYS_PP_NUM(lchip); pp_id++)
            {
                MCHIP_ACL(lchip)->set_league_global_config(lchip+pp_id, &config);
            }

            /*fid action config per level en*/
            config.fid_en = pacl_property->action_fid_en? 1: 0;
            config.op_type = SYS_ACL_LEAGUE_CONFIG_FID;
            for(pp_id = 0; pp_id < SYS_PP_NUM(lchip); pp_id++)
            {
                MCHIP_ACL(lchip)->set_league_global_config(lchip+pp_id, &config);
            }
        }

        cmd = DRV_IOR(IpeIntfMapperCtl_t, IpeIntfMapperCtl_bypassPktDoAclCtl_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!pacl_property->discard_pkt_lkup_en)
        {
            value |= 1;
        }
        else
        {
            value &= ~1;
        }
        cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_bypassPktDoAclCtl_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        /*acl*/
        if (DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOR(ProgramIngAclTcamLowPowerCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
            SetProgramIngAclTcamLowPowerCtl(V, enClkTcamSlice0_f + pacl_property->lkup_level*
                    (ProgramIngAclTcamLowPowerCtl_enClkTcamSlice1_f - ProgramIngAclTcamLowPowerCtl_enClkTcamSlice0_f), &ipe_fwd_acl, pacl_property->eco_en?0:1);
            cmd = DRV_IOW(ProgramIngAclTcamLowPowerCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
        }
        else if(DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(ProgramAclTcamLowPowerCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
            SetProgramAclTcamLowPowerCtl(V, enClkTcamSlice0_f + pacl_property->lkup_level*
                    (ProgramAclTcamLowPowerCtl_enClkTcamSlice1_f - ProgramAclTcamLowPowerCtl_enClkTcamSlice0_f), &ipe_fwd_acl, pacl_property->eco_en?0:1);
            cmd = DRV_IOW(ProgramAclTcamLowPowerCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
        }

       value = pacl_property->oam_pkt_lkup_disable ? 0 : 0xffff;
       cmd = DRV_IOW((DRV_FROM_TM(lchip) ? IpeAclQosCtl_t : IpeFwdCtl_t), (DRV_FROM_TM(lchip) ? IpeAclQosCtl_oamObeyAclQos_f : IpeFwdCtl_oamObeyAclQos_f));
       CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
   }

    for (loop=SYS_PP_BASE(lchip); loop<SYS_PP_BASE(lchip)+SYS_PP_NUM(lchip); loop++)
    {
        CTC_ERROR_RETURN(SYS_CB(SYS_CB_ACL_OP_GLB_PRESEL_EN, loop, pacl_property->glb_acl_presel_en, NULL));
    }

    SetFlowTcamLookupCtl(V, acl80bitKeyUseCvlan_f,&flow_ctl, pacl_property->key_ctag_en? 1 : 0);
    SetFlowTcamLookupCtl(V, aclForwardingBasicKeyUseCvlan_f,&flow_ctl, pacl_property->key_ctag_en? 1 : 0);
    SetFlowTcamLookupCtl(V, coppBasicKeyUseCtag_f,&flow_ctl, pacl_property->key_ctag_en? 1 : 0);
    SetFlowTcamLookupCtl(V, coppExtKeyUseCtag_f,&flow_ctl, pacl_property->key_ctag_en? 1 : 0);
    fwd_ext_key_u1_bmp = GetFlowTcamLookupCtl(V, forwardingAclKeyUnion1Type_f, &flow_ctl);
    if (pacl_property->fwd_ext_key_l2_hdr_en)
    {
        CTC_BIT_UNSET(fwd_ext_key_u1_bmp, pacl_property->lkup_level);
    }
    else
    {
        CTC_BIT_SET(fwd_ext_key_u1_bmp, pacl_property->lkup_level);
    }
    SetFlowTcamLookupCtl(V, forwardingAclKeyUnion1Type_f, &flow_ctl, fwd_ext_key_u1_bmp);
    SetFlowTcamLookupCtl(V, aclMacL3BasicKeyArpPktUseSenderMac_f, &flow_ctl, pacl_property->key_use_arp_sender_mac ? 1:0);
    SetFlowTcamLookupCtl(V, aclMacL3BasicKeyArpPktUseTargetMac_f, &flow_ctl, pacl_property->key_use_arp_target_mac ? 1:0);
    SetFlowTcamLookupCtl(V, aclMacL3ExtKeyArpPktUseSenderMac_f, &flow_ctl, pacl_property->key_use_arp_sender_mac ? 1:0);
    SetFlowTcamLookupCtl(V, aclMacL3ExtKeyArpPktUseTargetMac_f, &flow_ctl, pacl_property->key_use_arp_target_mac ? 1:0);
    SetFlowTcamLookupCtl(V, coppBasicKeyDisableArpShareMacDa_f, &flow_ctl, pacl_property->key_use_arp_target_mac ? 0:1);

    if ((SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) && DRV_IS_TSINGMA(lchip))
    {
        fwd_ext_key_u1_bmp = pacl_property->copp_key_fid_en ? 1: 0;
        SetFlowTcamLookupCtl(V, coppBasicKeySupportVsi_f, &flow_ctl, fwd_ext_key_u1_bmp);
        SetFlowTcamLookupCtl(V, coppExtKeySupportVsi_f, &flow_ctl, fwd_ext_key_u1_bmp);
        fwd_ext_key_u1_bmp = pacl_property->fwd_key_fid_en ? 1: 0;
        SetFlowTcamLookupCtl(V, forwardingBasicKeySupportVsi_f, &flow_ctl, fwd_ext_key_u1_bmp);
        SetFlowTcamLookupCtl(V, forwardingExtKeySupportVsi_f, &flow_ctl, fwd_ext_key_u1_bmp);

        value = pacl_property->l2l3_key_fid_en ? 1: 0;
        step = FlowTcamLookupCtl_gIngrAcl_1_aclL2L3KeySupportVsi_f - FlowTcamLookupCtl_gIngrAcl_0_aclL2L3KeySupportVsi_f;
        SetFlowTcamLookupCtl(V, gIngrAcl_0_aclL2L3KeySupportVsi_f + step*pacl_property->lkup_level , &flow_ctl, value);

    }

    if(pacl_property->dir == CTC_EGRESS || pacl_property->dir == CTC_BOTH_DIRECTION)
    {
        CTC_MAX_VALUE_CHECK(pacl_property->lkup_level,MCHIP_CAP(SYS_CAP_ACL_EGRESS_LKUP_NUM)-1);

        if (!DRV_FROM_TMM(lchip))
        {
            CTC_MAX_VALUE_CHECK(pacl_property->random_log_pri, MCHIP_CAP(SYS_CAP_ACL_EGRESS_LKUP_NUM)-1);
        }

        cmd = DRV_IOR(EpeAclQosCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_acl_ctl));
        cmd = DRV_IOR(EpePktProcCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_pkt_proc_ctl));
        value = GetEpeAclQosCtl(V, dropPktDisableAcl_f,&epe_acl_ctl);
        if(!pacl_property->discard_pkt_lkup_en)
        {
            CTC_BIT_SET(value ,pacl_property->lkup_level);
        }
        else
        {
            CTC_BIT_UNSET(value ,pacl_property->lkup_level);
        }
        SetEpeAclQosCtl(V, dropPktDisableAcl_f, &epe_acl_ctl,value);

        value = pacl_property->oam_pkt_lkup_disable ? 0 : 0xffff;
        SetEpeAclQosCtl(V, oamObeyAclQos_f, &epe_acl_ctl,value);

        DRV_SET_FLD_V2(lchip, EpeAclQosCtl_t, "gLookup_0_dropPktDisableAcl", &epe_acl_ctl, pacl_property->discard_pkt_lkup_en? 0: 3, "_0_", pacl_property->lkup_level);

        value = 0;
        for (loop = 0; loop < MAX_CTC_PARSER_L3_TYPE; loop++ )
        {
            if (pacl_property->l2l3_ext_key_use_l2l3_key[loop])
            {
                CTC_BIT_SET(value, loop);
            }
            else
            {
                CTC_BIT_UNSET(value, loop);
            }
        }
        SetEpeAclQosCtl(V, aclForceL2L3ExtKeyToL2L3Key_f, &epe_acl_ctl, value);
        SetEpeAclQosCtl(V, aclForceL3BasicV6ToL3ExtV6_f, &epe_acl_ctl, pacl_property->l3_key_ipv6_use_compress_addr?0:1);
        /*random log priority*/
        if (!DRV_FROM_TMM(lchip))
        {
            step = EpeAclQosCtl_aclLogSelectMap_1_logBlockNum_f - EpeAclQosCtl_aclLogSelectMap_0_logBlockNum_f;
            SetEpeAclQosCtl(V, aclLogSelectMap_0_logBlockNum_f+step*pacl_property->lkup_level, &epe_acl_ctl, pacl_property->random_log_pri);
        }
        cmd = DRV_IOW(EpeAclQosCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_acl_ctl));

        /*AT*/
        cmd = DRV_IOR(EpeAclQosCtl2_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_acl_ctl));
        SetEpeAclQosCtl2(V, gLookup_0_dropPktDisableAcl_f+pacl_property->lkup_level, &epe_acl_ctl, pacl_property->discard_pkt_lkup_en? 0: 3);
        cmd = DRV_IOW(EpeAclQosCtl2_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_acl_ctl));

        /*v6 basic key*/
        DRV_SET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_v6BasicKeyMode0IpAddr1Encode", &flow_ctl, pacl_property->key_ipv6_da_addr_mode, "_0_", pacl_property->lkup_level);
        DRV_SET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_v6BasicKeyMode0IpAddr2Encode", &flow_ctl, pacl_property->key_ipv6_sa_addr_mode, "_0_", pacl_property->lkup_level);

        /*fwd basic key*/
        step = FlowTcamLookupCtl_gEgrAcl_1_v6ForwardBasicKeyMode0IpAddr1Encode_f -
                FlowTcamLookupCtl_gEgrAcl_0_v6ForwardBasicKeyMode0IpAddr1Encode_f;
        SetFlowTcamLookupCtl(V, gEgrAcl_0_v6ForwardBasicKeyMode0IpAddr1Encode_f + pacl_property->lkup_level *step,
                                  &flow_ctl, pacl_property->key_ipv6_da_addr_mode);
        SetFlowTcamLookupCtl(V, gEgrAcl_0_v6ForwardBasicKeyMode0IpAddr2Encode_f + pacl_property->lkup_level *step,
                                  &flow_ctl, pacl_property->key_ipv6_sa_addr_mode);
        /*cid key*/
        SetFlowTcamLookupCtl(V, egrSgaclKeyIpv6DaAddrEncode_f,&flow_ctl, pacl_property->cid_key_ipv6_da_addr_mode);
        SetFlowTcamLookupCtl(V, egrSgaclKeyIpv6SaAddrEncode_f,&flow_ctl, pacl_property->cid_key_ipv6_sa_addr_mode);
        if((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
        {
            SetFlowTcamLookupCtl(V, aclMacIpv6KeyShare0Type_f,&flow_ctl, pacl_property->mac_ipv6_key_u0_mode);
            SetFlowTcamLookupCtl(V, aclMacIpv6KeyShare1Type_f,&flow_ctl, pacl_property->mac_ipv6_key_u1_mode);
        }

        /*CID enable*/
        step = FlowTcamLookupCtl_gEgrAcl_1_categoryIdFieldValid_f -
                FlowTcamLookupCtl_gEgrAcl_0_categoryIdFieldValid_f;
        switch(pacl_property->key_cid_mode)
        {
            case CTC_GLOBAL_ACL_CID_MODE_SRC:
                key_cid_valid = 2;
                break;
            case CTC_GLOBAL_ACL_CID_MODE_DST:
                key_cid_valid = 3;
                break;
            case CTC_GLOBAL_ACL_CID_MODE_SRC_DST:
            default:
                key_cid_valid = 0;
                break;
        }
        key_cid_valid = DRV_FROM_TMM(lchip)? key_cid_valid: 1;
        SetFlowTcamLookupCtl(V, gEgrAcl_0_categoryIdFieldValid_f + pacl_property->lkup_level *step,
                                  &flow_ctl, pacl_property->key_cid_en? key_cid_valid : (DRV_FROM_TMM(lchip)?1:0));
        value = ((pacl_property->key_use_arp_target_mac?1:0) << 1)|(pacl_property->key_use_arp_sender_mac?1:0);
        SetFlowTcamLookupCtl(V, aclMacKeyArpPktUseMacField_f, &flow_ctl, value);
        SetFlowTcamLookupCtl(V, aclMacL3BasicKeyArpPktUseMacField_f, &flow_ctl, value);
        SetFlowTcamLookupCtl(V, aclMacL3ExtKeyArpPktUseMacField_f, &flow_ctl, value);
        if (pacl_property->key_stk_hdr_en)
        {
            SetFlowTcamLookupCtl(V, aclMacKeyUseMacShareMode_f, &flow_ctl, 2);  /*default use mac sa*/
            DRV_SET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_l3Key160ShareFieldType", &flow_ctl, 0, "_0_", pacl_property->lkup_level);
            DRV_SET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_macL3BasicKeyU2Type", &flow_ctl, 1, "_0_", pacl_property->lkup_level);
            DRV_SET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_macL3BasicKeyU3Type", &flow_ctl, 1, "_0_", pacl_property->lkup_level);
        }
        else
        {
            SetFlowTcamLookupCtl(V, aclMacKeyUseMacShareMode_f, &flow_ctl, 0);
            DRV_SET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_l3Key160ShareFieldType", &flow_ctl, 2, "_0_", pacl_property->lkup_level);
            DRV_SET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_macL3BasicKeyU2Type", &flow_ctl, pacl_property->npm_im_en?3: pacl_property->l2l3_key_u2_mode, "_0_", pacl_property->lkup_level);
            DRV_SET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_macL3BasicKeyU3Type", &flow_ctl, pacl_property->l2l3_key_u3_mode, "_0_", pacl_property->lkup_level);
        }

        SetEpePktProcCtl(V, layer2TypeUsedAsVlanNum_f, &epe_pkt_proc_ctl, pacl_property->l2_type_as_vlan_num?1:0);
        cmd = DRV_IOW(EpePktProcCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_pkt_proc_ctl));
        /*acl*/
        if (DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOR(ProgramEgrAclTcamLowPowerCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
            SetProgramEgrAclTcamLowPowerCtl(V, enClkTcamSlice0_f + pacl_property->lkup_level*
                (ProgramEgrAclTcamLowPowerCtl_enClkTcamSlice1_f - ProgramEgrAclTcamLowPowerCtl_enClkTcamSlice0_f), &ipe_fwd_acl, pacl_property->eco_en?0:1);
            cmd = DRV_IOW(ProgramEgrAclTcamLowPowerCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
        }
        
  }
    cmd = DRV_IOW(FlowTcamLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &flow_ctl));

    if (MCHIP_MISC(lchip)->map_discard_type)
    {
        MCHIP_MISC(lchip)->map_discard_type(lchip, pacl_property->dir, pacl_property->drop_reason_en);
    }

    return CTC_E_NONE;
}

int32
sys_usw_set_glb_acl_property(uint8 lchip, ctc_global_acl_property_t* pacl_property, uint8 inner)
{
    uint8  loop = 0;
    uint8  acl_block_id = 0;
    uint8  acl_block_num = 0;
    uint8  acl_block_list[CTC_MAX_ACL_LKUP_NUM] = {0};
    uint8  acl_egs_block_num = 0;
    uint8  acl_egs_block_list[CTC_MAX_ACL_LKUP_NUM] = {0};
    uint8  dir;
    uint8 lkup_level;

    CTC_PTR_VALID_CHECK(pacl_property);
    CTC_MAX_VALUE_CHECK(pacl_property->dir,CTC_BOTH_DIRECTION);
    CTC_MAX_VALUE_CHECK(pacl_property->key_cid_en,1);
    CTC_MAX_VALUE_CHECK(pacl_property->discard_pkt_lkup_en,1);
    CTC_MAX_VALUE_CHECK(pacl_property->npm_im_en,1);
    CTC_MAX_VALUE_CHECK(pacl_property->key_ipv6_da_addr_mode,CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_16);
    CTC_MAX_VALUE_CHECK(pacl_property->key_ipv6_sa_addr_mode,CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_16);
    CTC_MAX_VALUE_CHECK(pacl_property->cid_key_ipv6_da_addr_mode,CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_16);
    CTC_MAX_VALUE_CHECK(pacl_property->cid_key_ipv6_sa_addr_mode,CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_16);
    CTC_MAX_VALUE_CHECK(pacl_property->key_cid_mode,CTC_GLOBAL_ACL_CID_MODE_MAX);
    CTC_MAX_VALUE_CHECK(pacl_property->mac_ipv6_key_u0_mode,SYS_USW_MAC_IPV6_KEY_U0_MODE_MAX);
    CTC_MAX_VALUE_CHECK(pacl_property->mac_ipv6_key_u1_mode,SYS_USW_MAC_IPV6_KEY_U1_MODE_MAX);
    CTC_MAX_VALUE_CHECK(pacl_property->l2l3_key_u2_mode,SYS_USW_L2L3_KEY_U2_MODE_MAX);
    CTC_MAX_VALUE_CHECK(pacl_property->l2l3_key_u3_mode,SYS_USW_L2L3_KEY_U3_MODE_MAX);

    if (DRV_FROM_AT(lchip) && pacl_property->npm_im_en)
    {
        return CTC_E_NOT_SUPPORT;
    }

    dir = pacl_property->dir;
    lkup_level = pacl_property->lkup_level;

    if(inner)
    {
        acl_block_num = 1;
        acl_block_list[0] = pacl_property->lkup_level;
    }
    else if(pacl_property->dir == CTC_BOTH_DIRECTION)
    {
        CTC_MAX_VALUE_CHECK(pacl_property->lkup_level, MCHIP_CAP(SYS_CAP_ACL_EGRESS_LKUP_NUM)-1);
        acl_block_id = pacl_property->lkup_level;/*ingress */
        pacl_property->dir = CTC_INGRESS;
        acl_block_num = sys_usw_acl_get_league_block(lchip, acl_block_id, acl_block_list);
        acl_block_id = pacl_property->lkup_level + MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM);/*egress */
        acl_egs_block_num = sys_usw_acl_get_league_block(lchip, acl_block_id, acl_egs_block_list);
    }
    else if(pacl_property->dir == CTC_INGRESS)
    {
        acl_block_id = pacl_property->lkup_level;
        acl_block_num = sys_usw_acl_get_league_block(lchip, acl_block_id, acl_block_list);
    }
    else
    {
        acl_block_id = pacl_property->lkup_level + MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM);
        acl_egs_block_num = sys_usw_acl_get_league_block(lchip, acl_block_id, acl_egs_block_list);
    }

    for (loop=0; loop<acl_block_num; loop++)
    {/* inner.both.ingress */
        pacl_property->lkup_level = acl_block_list[loop];
        CTC_ERROR_RETURN(_sys_usw_set_glb_acl_property(lchip, pacl_property, inner));
    }
    for (loop=0; loop<acl_egs_block_num; loop++)
    {/* both.egress */
        pacl_property->dir = CTC_EGRESS;
        pacl_property->lkup_level = acl_egs_block_list[loop];
        CTC_ERROR_RETURN(_sys_usw_set_glb_acl_property(lchip, pacl_property, inner));
    }

    pacl_property->lkup_level = lkup_level;
    pacl_property->dir = dir;

    return CTC_E_NONE;
}


int32
sys_usw_get_glb_acl_property(uint8 lchip, ctc_global_acl_property_t* pacl_property, uint8 inner)
{

    uint32 cmd = 0;
    uint32 value = 0;
    uint8  loop = 0;
    uint8  step = 0;
    uint8 fwd_ext_key_u1_bmp = 0;
    FlowTcamLookupCtl_m  flow_ctl;
    ds1_t ipe_fwd_acl;

    SYS_REGISTER_INIT_CHECK;
    CTC_PTR_VALID_CHECK(pacl_property);
    cmd = DRV_IOR(FlowTcamLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &flow_ctl));
    pacl_property->key_ctag_en =  GetFlowTcamLookupCtl(V, acl80bitKeyUseCvlan_f,&flow_ctl);
    fwd_ext_key_u1_bmp = GetFlowTcamLookupCtl(V, forwardingAclKeyUnion1Type_f, &flow_ctl);
    pacl_property->fwd_ext_key_l2_hdr_en = CTC_IS_BIT_SET(fwd_ext_key_u1_bmp, pacl_property->lkup_level)? 0: 1;

    if ((SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) && DRV_IS_TSINGMA(lchip))
    {
        pacl_property->copp_key_fid_en = GetFlowTcamLookupCtl(V, coppBasicKeySupportVsi_f, &flow_ctl);
        pacl_property->fwd_key_fid_en = GetFlowTcamLookupCtl(V, forwardingBasicKeySupportVsi_f, &flow_ctl);

        step = FlowTcamLookupCtl_gIngrAcl_1_aclL2L3KeySupportVsi_f - FlowTcamLookupCtl_gIngrAcl_0_aclL2L3KeySupportVsi_f;
        pacl_property->l2l3_key_fid_en = GetFlowTcamLookupCtl(V, gIngrAcl_0_aclL2L3KeySupportVsi_f + step*pacl_property->lkup_level , &flow_ctl);
    }

    if(!DRV_FROM_TMM(lchip))
    {
        pacl_property->key_use_arp_sender_mac = GetFlowTcamLookupCtl(V, aclMacL3BasicKeyArpPktUseSenderMac_f, &flow_ctl);
        pacl_property->key_use_arp_target_mac = GetFlowTcamLookupCtl(V, aclMacL3BasicKeyArpPktUseTargetMac_f, &flow_ctl);
    }
    SYS_CB(SYS_CB_ACL_OP_GLB_PRESEL_EN, lchip, 0, &pacl_property->glb_acl_presel_en);

    if(pacl_property->dir == CTC_INGRESS )
    {
        IpePreLookupAclCtl_m ipe_acl_ctl;
        IpeAclQosCtl_m       ipe_aclqos_ctl;

        /*AT*/
        cmd = DRV_IOR(IpeFwdAclCtl2_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
        value = GetIpeFwdAclCtl2(V, gLookup_0_dropPktDisableAcl_f + pacl_property->lkup_level, &ipe_fwd_acl);
        pacl_property->discard_pkt_lkup_en = (value==0? 1: 0);

        cmd = DRV_IOR(IpeFwdAclCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
        cmd = DRV_IOR(IpeAclQosCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_aclqos_ctl));

        CTC_MAX_VALUE_CHECK(pacl_property->lkup_level, MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM)-1);

        if ( DRV_FROM_TMM(lchip))
        {
            uint32 field_val = 0;
            uint8 step = IpeCflexAclCtl_cflexAcllkpLevel_1_cflexAclEnable_f - IpeCflexAclCtl_cflexAcllkpLevel_0_cflexAclEnable_f;

            cmd = DRV_IOR(IpeCflexAclCtl_t, IpeCflexAclCtl_cflexAcllkpLevel_0_cflexAclEnable_f + pacl_property->lkup_level*step);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            pacl_property->stk_hdr_lkup_en = field_val;

            if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
            {
                value = GetIpeFwdAclCtl(V, gLookup_0_dropPktDisableAcl_f + pacl_property->lkup_level, &ipe_fwd_acl);
                pacl_property->discard_pkt_lkup_en = (value==0? 1: 0);
            }

            value = GetIpeAclQosCtl(V, mplsInBandOamLevelEn_f, &ipe_aclqos_ctl);
            pacl_property->npm_im_en = CTC_IS_BIT_SET(value, pacl_property->lkup_level);
            value = GetIpeAclQosCtl(V, vxlanCompatibilityMode_f, &ipe_aclqos_ctl);
            pacl_property->action_fid_en = CTC_IS_BIT_SET(value, pacl_property->lkup_level);
            if (!inner)
            {
                CTC_ERROR_RETURN(sys_usw_acl_get_action_priority(lchip, pacl_property->lkup_level, &pacl_property->action_pri));
            }
        }
        else
        {
            value = GetIpeFwdAclCtl(V, dropPktDisableAcl_f, &ipe_fwd_acl);
            pacl_property->discard_pkt_lkup_en = !CTC_IS_BIT_SET(value, pacl_property->lkup_level);

            /*v6 basic key*/
            step = FlowTcamLookupCtl_gIngrAcl_1_v6BasicKeyMode0IpAddr1Encode_f -
                    FlowTcamLookupCtl_gIngrAcl_0_v6BasicKeyMode0IpAddr1Encode_f;
            pacl_property->key_ipv6_da_addr_mode = GetFlowTcamLookupCtl(V, gIngrAcl_0_v6BasicKeyMode0IpAddr1Encode_f + pacl_property->lkup_level *step,
                                                    &flow_ctl);
            pacl_property->key_ipv6_sa_addr_mode = GetFlowTcamLookupCtl(V, gIngrAcl_0_v6BasicKeyMode0IpAddr2Encode_f + pacl_property->lkup_level *step,
                                                    &flow_ctl);
            /*fwd basic key*/
            step = FlowTcamLookupCtl_gIngrAcl_1_v6ForwardBasicKeyMode0IpAddr1Encode_f -
                    FlowTcamLookupCtl_gIngrAcl_0_v6ForwardBasicKeyMode0IpAddr1Encode_f;
            pacl_property->key_ipv6_da_addr_mode = GetFlowTcamLookupCtl(V, gIngrAcl_0_v6ForwardBasicKeyMode0IpAddr1Encode_f + pacl_property->lkup_level *step,
                                                    &flow_ctl);
            pacl_property->key_ipv6_sa_addr_mode = GetFlowTcamLookupCtl(V, gIngrAcl_0_v6ForwardBasicKeyMode0IpAddr2Encode_f + pacl_property->lkup_level *step,
                                                    &flow_ctl);
            /*cid key*/
            pacl_property->cid_key_ipv6_da_addr_mode = GetFlowTcamLookupCtl(V, ingrSgaclKeyIpv6DaAddrEncode_f,&flow_ctl);
            pacl_property->cid_key_ipv6_sa_addr_mode = GetFlowTcamLookupCtl(V, ingrSgaclKeyIpv6SaAddrEncode_f, &flow_ctl );

            /*CID enable*/
            step = FlowTcamLookupCtl_gIngrAcl_1_categoryIdFieldValid_f -
                   FlowTcamLookupCtl_gIngrAcl_0_categoryIdFieldValid_f;
            pacl_property->key_cid_en = GetFlowTcamLookupCtl(V, gIngrAcl_0_categoryIdFieldValid_f + pacl_property->lkup_level *step,
                                                             &flow_ctl );
            /*Copp use udf*/
            pacl_property->copp_key_use_udf = GetFlowTcamLookupCtl(V, coppBasicKeyUseUdfShareType_f,&flow_ctl)?1:0;
            pacl_property->copp_ext_key_use_udf = GetFlowTcamLookupCtl(V, coppExtKeyUdfShareType_f,&flow_ctl)?0:1;

            /*random log priority*/
            if (!DRV_FROM_TMM(lchip))
            {
                step = IpeAclQosCtl_aclLogSelectMap_1_logBlockNum_f - IpeAclQosCtl_aclLogSelectMap_0_logBlockNum_f;
                pacl_property->random_log_pri = GetIpeAclQosCtl(V, aclLogSelectMap_0_logBlockNum_f+step*pacl_property->lkup_level, &ipe_aclqos_ctl);
            }
        }

        cmd = DRV_IOR((DRV_FROM_TM(lchip) ? IpeAclQosCtl_t : IpeFwdCtl_t), (DRV_FROM_TM(lchip) ? IpeAclQosCtl_oamObeyAclQos_f : IpeFwdCtl_oamObeyAclQos_f));
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        pacl_property->oam_pkt_lkup_disable = !value;

        value = DRV_FROM_TMM(lchip) ? GetIpeFwdAclCtl(V, useCoppExtKey_f, &ipe_fwd_acl) : GetIpeFwdAclCtl(V, useCopp640bitsKey_f, &ipe_fwd_acl);
        for (loop = 0; loop < MAX_CTC_PARSER_L3_TYPE; loop++ )
        {
            pacl_property->copp_key_use_ext_mode[loop] = CTC_IS_BIT_SET(value, loop);
        }
        value = GetIpeFwdAclCtl(V, aclForceL2L3ExtKeyToL2L3Key_f, &ipe_fwd_acl);
        for (loop = 0; loop < MAX_CTC_PARSER_L3_TYPE; loop++ )
        {
            pacl_property->l2l3_ext_key_use_l2l3_key[loop] =  CTC_IS_BIT_SET(value, loop);
        }

        pacl_property->l3_key_ipv6_use_compress_addr = !GetIpeFwdAclCtl(V, aclForceL3BasicV6ToL3ExtV6_f, &ipe_fwd_acl);

        if ((SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) && DRV_IS_TSINGMA(lchip))
        {
            cmd = DRV_IOR(IpeAclReserved_t, IpeAclReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            pacl_property->action_fid_en = (value >> pacl_property->lkup_level)&0x1;
        }

        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(IpeFwdAclCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
            pacl_property->stp_blocked_pkt_lkup_en = GetIpeFwdAclCtl(V, bridgePktAclObeyStpBlock_f, &ipe_fwd_acl)?0:1;
            pacl_property->l2_type_as_vlan_num = 0;
        }
        else
        {
            cmd = DRV_IOR(IpePreLookupAclCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_acl_ctl));
            pacl_property->stp_blocked_pkt_lkup_en = GetIpePreLookupAclCtl(V, bridgePktAclObeyStpBlock_f, &ipe_acl_ctl)?0:1;
            pacl_property->l2_type_as_vlan_num = GetIpePreLookupAclCtl(V, layer2TypeUsedAsVlanNum_f, &ipe_acl_ctl)?1:0;
        }

        if (DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOR(ProgramIngAclTcamLowPowerCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
            pacl_property->eco_en = GetProgramIngAclTcamLowPowerCtl(V, enClkTcamSlice0_f + pacl_property->lkup_level*
                    (ProgramIngAclTcamLowPowerCtl_enClkTcamSlice1_f - ProgramIngAclTcamLowPowerCtl_enClkTcamSlice0_f), &ipe_fwd_acl)?0:1;
        }
        else if(DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(ProgramAclTcamLowPowerCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
            pacl_property->eco_en = GetProgramAclTcamLowPowerCtl(V, enClkTcamSlice0_f + pacl_property->lkup_level*
                    (ProgramAclTcamLowPowerCtl_enClkTcamSlice1_f - ProgramAclTcamLowPowerCtl_enClkTcamSlice0_f), &ipe_fwd_acl)?0:1;
        }
        
    }
    else if(pacl_property->dir == CTC_EGRESS )
    {
        EpePktProcCtl_m      epe_pkt_proc_ctl;
        CTC_MAX_VALUE_CHECK(pacl_property->lkup_level, MCHIP_CAP(SYS_CAP_ACL_EGRESS_LKUP_NUM)-1);
        if (DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOR(EpeAclQosCtl2_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_acl_ctl));
            value = GetEpeAclQosCtl2(V, gLookup_0_dropPktDisableAcl_f+pacl_property->lkup_level, &epe_acl_ctl);
            pacl_property->discard_pkt_lkup_en = value==0? 1: 0;
        }
        cmd = DRV_IOR(EpeAclQosCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_acl_ctl));

        if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
        {
            DRV_GET_FLD_V2(lchip, EpeAclQosCtl_t, "gLookup_0_dropPktDisableAcl", &epe_acl_ctl, value, "_0_", pacl_property->lkup_level);
            pacl_property->discard_pkt_lkup_en = value==0? 1: 0;
            pacl_property->key_use_arp_sender_mac = GetFlowTcamLookupCtl(V, aclMacKeyArpPktUseMacField_f, &flow_ctl) & 0x01;
            pacl_property->key_use_arp_target_mac = GetFlowTcamLookupCtl(V, aclMacKeyArpPktUseMacField_f, &flow_ctl) >> 1;
        }
        else if (!DRV_FROM_TMM(lchip))
        {
            value = GetEpeAclQosCtl(V,dropPktDisableAcl_f,&epe_acl_ctl);
            pacl_property->discard_pkt_lkup_en = !CTC_IS_BIT_SET(value,pacl_property->lkup_level);
        }
        pacl_property->l3_key_ipv6_use_compress_addr = !GetEpeAclQosCtl(V, aclForceL3BasicV6ToL3ExtV6_f, &epe_acl_ctl);
        pacl_property->oam_pkt_lkup_disable = !GetEpeAclQosCtl(V, oamObeyAclQos_f, &epe_acl_ctl);
        value = GetEpeAclQosCtl(V, aclForceL2L3ExtKeyToL2L3Key_f, &epe_acl_ctl);
        for (loop = 0; loop < MAX_CTC_PARSER_L3_TYPE; loop++ )
        {
            pacl_property->l2l3_ext_key_use_l2l3_key[loop] = CTC_IS_BIT_SET(value, loop);
        }

        /*fwd basic key*/
        step = FlowTcamLookupCtl_gEgrAcl_1_v6ForwardBasicKeyMode0IpAddr1Encode_f -
                FlowTcamLookupCtl_gEgrAcl_0_v6ForwardBasicKeyMode0IpAddr1Encode_f;
        pacl_property->key_ipv6_da_addr_mode = GetFlowTcamLookupCtl(V, gEgrAcl_0_v6ForwardBasicKeyMode0IpAddr1Encode_f + pacl_property->lkup_level *step,
                                                &flow_ctl);
        pacl_property->key_ipv6_sa_addr_mode = GetFlowTcamLookupCtl(V, gEgrAcl_0_v6ForwardBasicKeyMode0IpAddr2Encode_f + pacl_property->lkup_level *step,
                                                &flow_ctl);
        /*v6 basic key, must be after fwd basic key*/
        DRV_GET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_v6BasicKeyMode0IpAddr1Encode", &flow_ctl, pacl_property->key_ipv6_da_addr_mode, "_0_", pacl_property->lkup_level);
        DRV_GET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_v6BasicKeyMode0IpAddr2Encode", &flow_ctl, pacl_property->key_ipv6_sa_addr_mode, "_0_", pacl_property->lkup_level);

        /*cid key*/
        pacl_property->cid_key_ipv6_da_addr_mode = GetFlowTcamLookupCtl(V, egrSgaclKeyIpv6DaAddrEncode_f,&flow_ctl);
        pacl_property->cid_key_ipv6_sa_addr_mode = GetFlowTcamLookupCtl(V, egrSgaclKeyIpv6SaAddrEncode_f,&flow_ctl );

        /*CID enable*/
        step = FlowTcamLookupCtl_gEgrAcl_1_categoryIdFieldValid_f -
        FlowTcamLookupCtl_gEgrAcl_0_categoryIdFieldValid_f;
        pacl_property->key_cid_en = GetFlowTcamLookupCtl(V, gEgrAcl_0_categoryIdFieldValid_f + pacl_property->lkup_level *step, &flow_ctl);
        if (DRV_IS_TMM(lchip)||DRV_IS_TMG(lchip))
        {
            uint8 block_id = (CTC_INGRESS == pacl_property->dir) ? pacl_property->lkup_level : pacl_property->lkup_level+MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM);
            switch(pacl_property->key_cid_en)
            {
                case 0:
                    pacl_property->key_cid_mode = CTC_GLOBAL_ACL_CID_MODE_SRC_DST;
                    break;
                case 2:
                    pacl_property->key_cid_mode = CTC_GLOBAL_ACL_CID_MODE_SRC;
                    break;
                case 3:
                    pacl_property->key_cid_mode = CTC_GLOBAL_ACL_CID_MODE_DST;
                    break;
                default:
                    break;
            }
            pacl_property->key_cid_en = (pacl_property->key_cid_en!=1);
            if (!inner)
            {
                CTC_ERROR_RETURN(sys_usw_acl_get_action_priority(lchip, block_id, &pacl_property->action_pri));
            }
        }

        DRV_GET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_l3Key160ShareFieldType", &flow_ctl, value, "_0_", pacl_property->lkup_level);
        DRV_GET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_macL3BasicKeyU2Type", &flow_ctl, pacl_property->l2l3_key_u2_mode, "_0_", pacl_property->lkup_level);
        pacl_property->npm_im_en = (pacl_property->l2l3_key_u2_mode == 3) ? 1 : 0;
        DRV_GET_FLD_V2(lchip, FlowTcamLookupCtl_t, "gEgrAcl_0_macL3BasicKeyU3Type", &flow_ctl, pacl_property->l2l3_key_u3_mode, "_0_", pacl_property->lkup_level);
        pacl_property->mac_ipv6_key_u0_mode = GetFlowTcamLookupCtl(V, aclMacIpv6KeyShare0Type_f,&flow_ctl);
        pacl_property->mac_ipv6_key_u1_mode = GetFlowTcamLookupCtl(V, aclMacIpv6KeyShare1Type_f,&flow_ctl);

        if(0 == value && 1 == pacl_property->l2l3_key_u2_mode && 1 == pacl_property->l2l3_key_u3_mode && 2 == GetFlowTcamLookupCtl(V, aclMacKeyUseMacShareMode_f, &flow_ctl))
        {
            pacl_property->key_stk_hdr_en = 1;
            /* conflict, need set 0 */
            pacl_property->l2l3_key_u2_mode = 0;
            pacl_property->l2l3_key_u3_mode = 0;
            pacl_property->npm_im_en = 0;
        }

        /*random log priority*/
        if (!DRV_FROM_TMM(lchip))
        {
            step = EpeAclQosCtl_aclLogSelectMap_1_logBlockNum_f - EpeAclQosCtl_aclLogSelectMap_0_logBlockNum_f;
            pacl_property->random_log_pri = GetEpeAclQosCtl(V, aclLogSelectMap_0_logBlockNum_f+step*pacl_property->lkup_level, &epe_acl_ctl);
        }
        cmd = DRV_IOR(EpePktProcCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_pkt_proc_ctl));
        pacl_property->l2_type_as_vlan_num = GetEpePktProcCtl(V, layer2TypeUsedAsVlanNum_f, &epe_pkt_proc_ctl)?1:0;

        /*acl*/
        if (DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOR(ProgramEgrAclTcamLowPowerCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_acl));
            pacl_property->eco_en = GetProgramEgrAclTcamLowPowerCtl(V, enClkTcamSlice0_f + pacl_property->lkup_level*
                (ProgramEgrAclTcamLowPowerCtl_enClkTcamSlice1_f - ProgramEgrAclTcamLowPowerCtl_enClkTcamSlice0_f), &ipe_fwd_acl)?0:1;
        }
        
    }
    else
    {
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}
#undef epe_acl_ctl

#define SYS_CID_RES_CHK(cid_index)    if (cid_index>=4) CTC_ERROR_RETURN(CTC_E_INVALID_PARAM)
STATIC int32
_sys_usw_set_presel_cid(uint8 lchip, ctc_global_cid_property_t* pcid_property)
{

    int8   cid[4] = { -1, -1, -1, -1};
    uint8  cid_index = 0;
    uint8  loop = 0;
    uint32 cmd = 0;
    ProgramAclLtidSelectConfig_m config;
    uint32 config_table[CTC_BOTH_DIRECTION] = {ProgramAclLtidSelectConfig_t, EgrProgramAclLtidSelectConfig_t};

    if (CTC_FLAG_ISSET(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_PORT_CID))
    {
        cid[cid_index++] =  0;
    }

    if (CTC_FLAG_ISSET(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_VLAN_CID))
    {
        cid[cid_index++] =  1;
    }

    if (CTC_FLAG_ISSET(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_L3IF_CID))
    {
        cid[cid_index++] =  2;
    }

    if (CTC_FLAG_ISSET(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_SCL_CID))    /*egress, CTC_GLOBAL_PRESEL_NHP_CID*/
    {
        cid[cid_index++] =  3;
    }

    if (CTC_FLAG_ISSET(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_TUNNEL_CID)) /*egress, CTC_GLOBAL_PRESEL_I2E_CID*/
    {
        SYS_CID_RES_CHK(cid_index);
        cid[cid_index++] =  4;
    }

    if (pcid_property->dir == CTC_INGRESS)
    {
        if (CTC_FLAG_ISSET(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_FLOW_CID))
        {
            SYS_CID_RES_CHK(cid_index);
            cid[cid_index++] =  5;
        }

        if (CTC_FLAG_ISSET(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_FID_CID))
        {
            SYS_CID_RES_CHK(cid_index);
            cid[cid_index++] =  6;
        }
    }
    else
    {
        if (CTC_FLAG_ISSET(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_LDP_CID))
        {
            SYS_CID_RES_CHK(cid_index);
            cid[cid_index++] =  5;
        }
    }

    sal_memset(&config, 0, sizeof(config));

    for (loop = 0; loop < 4; loop++)
    {
        SetProgramAclLtidSelectConfig(V, categoryId0Sel_f + loop,  &config, (cid[loop] == -1) ? 7: cid[loop]);
    }

    cmd = DRV_IOW(config_table[pcid_property->dir], DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &config));


    return CTC_E_NONE;
}

STATIC int32
_sys_usw_get_presel_cid(uint8 lchip, ctc_global_cid_property_t* pcid_property)
{

    int8   cid[4] = { -1, -1, -1, -1};
    uint8  loop = 0;
    uint32 cmd = 0;
    ProgramAclLtidSelectConfig_m config;
    uint32 config_table[CTC_BOTH_DIRECTION] = {ProgramAclLtidSelectConfig_t, EgrProgramAclLtidSelectConfig_t};

    sal_memset(&config, 0, sizeof(config));
    cmd = DRV_IOR(config_table[pcid_property->dir], DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &config));

    for (loop = 0; loop < 4; loop++)
    {
        cid[loop] = GetProgramAclLtidSelectConfig(V, categoryId0Sel_f + loop,  &config);

        switch(cid[loop])
        {
        case 0:
            CTC_SET_FLAG(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_PORT_CID);
            break;
        case 1:
            CTC_SET_FLAG(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_VLAN_CID);
            break;
        case 2:
            CTC_SET_FLAG(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_L3IF_CID);
            break;
        case 3:
            CTC_SET_FLAG(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_SCL_CID);      /*egress, CTC_GLOBAL_PRESEL_NHP_CID*/
            break;
        case 4:
            CTC_SET_FLAG(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_TUNNEL_CID);   /*egress, CTC_GLOBAL_PRESEL_I2E_CID*/
            break;
        case 5:
            if (CTC_INGRESS == pcid_property->dir)
            {
                CTC_SET_FLAG(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_FLOW_CID);
            }
            else
            {
                CTC_SET_FLAG(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_LDP_CID);
            }
            break;
        case 6:
            CTC_SET_FLAG(pcid_property->presel_cid_bitmap, CTC_GLOBAL_PRESEL_FID_CID);
            break;

        default:
            break;
        }
    }

    return CTC_E_NONE;
}


STATIC int32
_sys_usw_set_glb_cid_property(uint8 lchip, ctc_global_cid_property_t* pcid_property)
{
    ParserEthernetCtl_m     cid_parser_ctl;
    IpeFwdCategoryCtl_m     cid_glb_ctl;
    EpeHeaderEditCtl_m      epe_edit_ctl;
    EpeNextHopCtl_m         epe_nh_ctl;
    uint32 cmd = 0;
    uint8 step = 0, loop = 0 ;
    uint32 field_val = 0;
    CTC_PTR_VALID_CHECK(pcid_property);

    if (pcid_property->global_cid_en)
    {
        SYS_USW_CID_CHECK(lchip, pcid_property->global_cid);
    }
    if (pcid_property->reassign_cid_pri_en)
    {
        if (!pcid_property->is_dst_cid)
       {
        CTC_MAX_VALUE_CHECK(pcid_property->pkt_cid_pri,7);
        CTC_MAX_VALUE_CHECK(pcid_property->iloop_cid_pri,7);
        CTC_MAX_VALUE_CHECK(pcid_property->global_cid_pri,7);
        CTC_MAX_VALUE_CHECK(pcid_property->flow_table_cid_pri,7);
        CTC_MAX_VALUE_CHECK(pcid_property->fwd_table_cid_pri,7);
        CTC_MAX_VALUE_CHECK(pcid_property->if_cid_pri,7);
        CTC_MAX_VALUE_CHECK(pcid_property->default_cid_pri,7);
       }
        else
        {
            CTC_MAX_VALUE_CHECK(pcid_property->flow_table_cid_pri,3);
            CTC_MAX_VALUE_CHECK(pcid_property->fwd_table_cid_pri,3);
            CTC_MAX_VALUE_CHECK(pcid_property->default_cid_pri,3);
        }
    }

    if (DRV_FROM_TMM(lchip))
    {
        CTC_ERROR_RETURN(_sys_usw_set_presel_cid(lchip, pcid_property));
    }

    field_val = (pcid_property->cross_chip_cid_en) ? 1:0;
    cmd = DRV_IOW(EpeHeaderEditCtl_t, EpeHeaderEditCtl_extCidValid_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    cmd = DRV_IOR(ParserEthernetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &cid_parser_ctl));
    SetParserEthernetCtl(V, supportMetaDataHeader_f, &cid_parser_ctl, pcid_property->cmd_parser_en?1:0);
    if(DRV_FROM_AT(lchip))
    {
        SetParserEthernetCtl(V, gL2ExtHdr_1_etherType_f, &cid_parser_ctl, pcid_property->cmd_ethtype);  
    }
    else
    {
        SetParserEthernetCtl(V, metaDataEtherType_f, &cid_parser_ctl, pcid_property->cmd_ethtype);
    }
    SetParserEthernetCtl(V, sgtEn_f, &cid_parser_ctl, pcid_property->cmd_parser_en?1:0);

    cmd = DRV_IOW(ParserEthernetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &cid_parser_ctl));

    cmd = DRV_IOR(EpeHeaderEditCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_edit_ctl));
    SetEpeHeaderEditCtl(V, cidHdrEtherType_f, &epe_edit_ctl, pcid_property->cmd_ethtype);
    cmd = DRV_IOW(EpeHeaderEditCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_edit_ctl));

    cmd = DRV_IOR(EpeNextHopCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_nh_ctl));
    SetEpeNextHopCtl(V, bypassInsertCidThreValid_f, &epe_nh_ctl, 1);
    SetEpeNextHopCtl(V, bypassInsertCidThre_f, &epe_nh_ctl, pcid_property->insert_cid_hdr_en ?255:0);
    cmd = DRV_IOW(EpeNextHopCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_nh_ctl));

    cmd = DRV_IOR(IpeFwdCategoryCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &cid_glb_ctl));
    SetIpeFwdCategoryCtl(V,globalSrcCategoryIdValid_f,&cid_glb_ctl,pcid_property->global_cid_en?1:0);
    SetIpeFwdCategoryCtl(V,globalSrcCategoryId_f,&cid_glb_ctl,pcid_property->global_cid);
    SetIpeFwdCategoryCtl(V,categoryIdPairLookupEn_f,&cid_glb_ctl,pcid_property->cid_pair_en?1:0);
    if(pcid_property->reassign_cid_pri_en)
    {
       if(!pcid_property->is_dst_cid)
       {
          step = IpeFwdCategoryCtl_gSrcCidPri_1_pktSrcCategoryIdPri_f -
                        IpeFwdCategoryCtl_gSrcCidPri_0_pktSrcCategoryIdPri_f;
          for(loop = 0; loop < 6 ;loop++)
          {
             SetIpeFwdCategoryCtl(V, gSrcCidPri_0_pktSrcCategoryIdPri_f + step *loop,     &cid_glb_ctl, pcid_property->pkt_cid_pri);
             SetIpeFwdCategoryCtl(V, gSrcCidPri_0_i2eSrcCategoryIdPri_f + step *loop,     &cid_glb_ctl, pcid_property->iloop_cid_pri);
             SetIpeFwdCategoryCtl(V, gSrcCidPri_0_globalSrcCategoryIdPri_f + step *loop,  &cid_glb_ctl, pcid_property->global_cid_pri);
             SetIpeFwdCategoryCtl(V, gSrcCidPri_0_staticSrcCategoryIdPri_f + step *loop,  &cid_glb_ctl, pcid_property->flow_table_cid_pri);
             SetIpeFwdCategoryCtl(V, gSrcCidPri_0_dynamicSrcCategoryIdPri_f + step *loop, &cid_glb_ctl, pcid_property->fwd_table_cid_pri);
             SetIpeFwdCategoryCtl(V, gSrcCidPri_0_ifSrcCategoryIdPri_f + step *loop,      &cid_glb_ctl, pcid_property->if_cid_pri);
             SetIpeFwdCategoryCtl(V, gSrcCidPri_0_defaultSrcCategoryIdPri_f+ step *loop, &cid_glb_ctl, pcid_property->default_cid_pri);
          }
       }
       else
       {
         SetIpeFwdCategoryCtl(V, gDstCidPri_defaultDstCategoryIdPri_f, &cid_glb_ctl, pcid_property->default_cid_pri);
         SetIpeFwdCategoryCtl(V, gDstCidPri_dsflowDstCategoryIdPri_f,  &cid_glb_ctl, pcid_property->flow_table_cid_pri);
         SetIpeFwdCategoryCtl(V, gDstCidPri_dynamicDstCategoryIdPri_f, &cid_glb_ctl, pcid_property->fwd_table_cid_pri);
         SetIpeFwdCategoryCtl(V, gDstCidPri_staticDstCategoryIdPri_f,  &cid_glb_ctl, pcid_property->flow_table_cid_pri);
       }

    }

  cmd = DRV_IOW(IpeFwdCategoryCtl_t, DRV_ENTRY_FLAG);
  CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &cid_glb_ctl));





  return CTC_E_NONE;
}

STATIC int32
_sys_usw_get_glb_cid_property(uint8 lchip, ctc_global_cid_property_t* pcid_property)
{
    ParserEthernetCtl_m     cid_parser_ctl;
    IpeFwdCategoryCtl_m      cid_glb_ctl;
    EpeNextHopCtl_m     epe_nh_ctl;
    uint32 cmd = 0;
    uint32 field_val = 0;
    CTC_PTR_VALID_CHECK(pcid_property);


    if (DRV_FROM_TMM(lchip))
    {
        CTC_ERROR_RETURN(_sys_usw_get_presel_cid(lchip, pcid_property));
    }

    cmd = DRV_IOR(ParserEthernetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &cid_parser_ctl));
    pcid_property->cmd_parser_en = GetParserEthernetCtl(V, supportMetaDataHeader_f, &cid_parser_ctl);
    if(DRV_FROM_AT(lchip))
    {
        pcid_property->cmd_ethtype = GetParserEthernetCtl(V, gL2ExtHdr_1_etherType_f, &cid_parser_ctl);  
    }
    else
    {
        pcid_property->cmd_ethtype = GetParserEthernetCtl(V, metaDataEtherType_f, &cid_parser_ctl);
    }
    cmd = DRV_IOR(IpeFwdCategoryCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &cid_glb_ctl));
    pcid_property->global_cid_en = GetIpeFwdCategoryCtl(V, globalSrcCategoryIdValid_f, &cid_glb_ctl);
    pcid_property->global_cid = GetIpeFwdCategoryCtl(V, globalSrcCategoryId_f, &cid_glb_ctl);
    pcid_property->cid_pair_en = GetIpeFwdCategoryCtl(V, categoryIdPairLookupEn_f, &cid_glb_ctl);
    cmd = DRV_IOR(EpeNextHopCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_nh_ctl));
    pcid_property->insert_cid_hdr_en = GetEpeNextHopCtl(V, bypassInsertCidThre_f, &epe_nh_ctl)?1:0;

    cmd = DRV_IOR(EpeHeaderEditCtl_t, EpeHeaderEditCtl_extCidValid_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    pcid_property->cross_chip_cid_en = field_val;

    if (!pcid_property->is_dst_cid)
    {
        pcid_property->pkt_cid_pri = GetIpeFwdCategoryCtl(V, gSrcCidPri_0_pktSrcCategoryIdPri_f, &cid_glb_ctl);
        pcid_property->iloop_cid_pri = GetIpeFwdCategoryCtl(V, gSrcCidPri_0_i2eSrcCategoryIdPri_f, &cid_glb_ctl);
        pcid_property->global_cid_pri = GetIpeFwdCategoryCtl(V, gSrcCidPri_0_globalSrcCategoryIdPri_f, &cid_glb_ctl);
        pcid_property->flow_table_cid_pri = GetIpeFwdCategoryCtl(V, gSrcCidPri_0_staticSrcCategoryIdPri_f, &cid_glb_ctl);
        pcid_property->fwd_table_cid_pri = GetIpeFwdCategoryCtl(V, gSrcCidPri_0_dynamicSrcCategoryIdPri_f, &cid_glb_ctl);
        pcid_property->if_cid_pri = GetIpeFwdCategoryCtl(V, gSrcCidPri_0_ifSrcCategoryIdPri_f, &cid_glb_ctl);
        pcid_property->default_cid_pri = GetIpeFwdCategoryCtl(V, gSrcCidPri_0_defaultSrcCategoryIdPri_f, &cid_glb_ctl);
    }
    else
    {
        pcid_property->default_cid_pri = GetIpeFwdCategoryCtl(V, gDstCidPri_defaultDstCategoryIdPri_f, &cid_glb_ctl);
        pcid_property->flow_table_cid_pri = GetIpeFwdCategoryCtl(V, gDstCidPri_dsflowDstCategoryIdPri_f, &cid_glb_ctl);
        pcid_property->fwd_table_cid_pri = GetIpeFwdCategoryCtl(V, gDstCidPri_dynamicDstCategoryIdPri_f, &cid_glb_ctl);
        pcid_property->flow_table_cid_pri = GetIpeFwdCategoryCtl(V, gDstCidPri_staticDstCategoryIdPri_f, &cid_glb_ctl);
    }

    return CTC_E_NONE;
}
STATIC int32
_sys_usw_set_glb_ipmc_property(uint8 lchip, ctc_global_ipmc_property_t* pipmc_property)
{
    uint32 cmd = 0;
    uint32 value = 0;

    CTC_PTR_VALID_CHECK(pipmc_property);
    CTC_MAX_VALUE_CHECK(pipmc_property->ip_l2mc_mode, 1);
    value = pipmc_property->ip_l2mc_mode;
    cmd = DRV_IOW(FibEngineLookupCtl_t, FibEngineLookupCtl_l2mcMacIpParallel_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_set_glb_acl_lkup_property(uint8 lchip, ctc_acl_property_t* acl_prop)
{
    uint32 cmd = 0;
    uint8  lkup_type = 0;
    uint8  gport_type = 0;
    uint8  max_block_num = acl_prop->direction == CTC_INGRESS ? MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM) : MCHIP_CAP(SYS_CAP_ACL_EGRESS_LKUP_NUM);
    ds1_t  ds;
    sys_register_glb_acl_lkup_t glb_acl_lkup;

    CTC_PTR_VALID_CHECK(acl_prop);
    SYS_USW_GLOBAL_ACL_PROP_CHK(acl_prop);
    SYS_USW_MAX_CLASS_ID_CHECK(acl_prop->class_id);
    CTC_MAX_VALUE_CHECK(acl_prop->acl_priority, max_block_num-1);
    sal_memset(&glb_acl_lkup, 0, sizeof(glb_acl_lkup));
    if(CTC_ACL_TCAM_LKUP_TYPE_VLAN == acl_prop->tcam_lkup_type)
    {
        return CTC_E_NOT_SUPPORT;
    }

    if(CTC_FLAG_ISSET(acl_prop->flag, CTC_ACL_PROP_FLAG_USE_HASH_LKUP))
    {
        return CTC_E_NOT_SUPPORT;
    }

    if(DRV_IS_TMM(lchip) && acl_prop->acl_en && acl_prop->direction != CTC_INGRESS && 
        (acl_prop->tcam_lkup_type >= CTC_ACL_TCAM_LKUP_TYPE_CID))
    {
        return CTC_E_NOT_SUPPORT;
    }

    lkup_type = sys_usw_map_acl_tcam_lkup_type(lchip, acl_prop->tcam_lkup_type);
    if(CTC_FLAG_ISSET(acl_prop->flag, CTC_ACL_PROP_FLAG_USE_PORT_BITMAP))
    {
        gport_type = DRV_ENUM(DRV_FLOWPORTTYPE_BITMAP);
    }
    else if(CTC_FLAG_ISSET(acl_prop->flag, CTC_ACL_PROP_FLAG_USE_METADATA))
    {
        gport_type = DRV_ENUM(DRV_FLOWPORTTYPE_METADATA);
    }
    else if(CTC_FLAG_ISSET(acl_prop->flag, CTC_ACL_PROP_FLAG_USE_LOGIC_PORT))
    {
        gport_type = DRV_ENUM(DRV_FLOWPORTTYPE_LPORT);
    }
    else
    {
        gport_type = DRV_ENUM(DRV_FLOWPORTTYPE_GPORT);
    }

    if (MCHIP_MISC(lchip)->register_get_glb_acl_table)
    {
        MCHIP_MISC(lchip)->register_get_glb_acl_table(lchip, acl_prop->direction, &glb_acl_lkup);
    }
    cmd = DRV_IOR(glb_acl_lkup.table_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    if (acl_prop->acl_en)
    {
        DRV_SET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_enable + acl_prop->acl_priority, &ds, 1);
        DRV_SET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_label + acl_prop->acl_priority, &ds, acl_prop->class_id);
        DRV_SET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_lkup_type + acl_prop->acl_priority, &ds, lkup_type);
        DRV_SET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_gport_type + acl_prop->acl_priority, &ds, gport_type);
        DRV_SET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_use_pi_vlan + acl_prop->acl_priority, &ds,
                        CTC_FLAG_ISSET(acl_prop->flag, CTC_ACL_PROP_FLAG_USE_MAPPED_VLAN)?1:0);
        SetIpePreLookupAclCtl(V, gGlbAcl_0_aclUseCapwapInfo_f + acl_prop->acl_priority,  &ds,
                        CTC_FLAG_ISSET(acl_prop->flag, CTC_ACL_PROP_FLAG_USE_WLAN)?1:0);
    }
    else
    {
        DRV_SET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_enable + acl_prop->acl_priority, &ds, 0);
        DRV_SET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_label + acl_prop->acl_priority, &ds, 0);
        DRV_SET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_lkup_type + acl_prop->acl_priority, &ds, 0);
        DRV_SET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_gport_type + acl_prop->acl_priority, &ds, 0);
        DRV_SET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_use_pi_vlan + acl_prop->acl_priority, &ds, 0);
        SetIpePreLookupAclCtl(V, gGlbAcl_0_aclUseCapwapInfo_f + acl_prop->acl_priority,  &ds, 0);
    }

    cmd = DRV_IOW(glb_acl_lkup.table_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_get_glb_acl_lkup_property(uint8 lchip, ctc_acl_property_t* acl_prop)
{
    uint32 cmd = 0;
    uint8  lkup_type = 0;
    uint8  gport_type = 0;
    uint8  use_mapped_vlan = 0;
    uint8  use_wlan = 0;
    uint8  max_block_num = acl_prop->direction == CTC_INGRESS ? MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM) : MCHIP_CAP(SYS_CAP_ACL_EGRESS_LKUP_NUM);
    ds1_t  ds;
    sys_register_glb_acl_lkup_t glb_acl_lkup;

    CTC_PTR_VALID_CHECK(acl_prop);
    CTC_MAX_VALUE_CHECK(acl_prop->direction, CTC_EGRESS);
    CTC_MAX_VALUE_CHECK(acl_prop->acl_priority, max_block_num-1);
    sal_memset(&glb_acl_lkup, 0, sizeof(glb_acl_lkup));
    if (MCHIP_MISC(lchip)->register_get_glb_acl_table)
    {
        MCHIP_MISC(lchip)->register_get_glb_acl_table(lchip, acl_prop->direction, &glb_acl_lkup);
    }
    cmd = DRV_IOR(glb_acl_lkup.table_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    acl_prop->acl_en =      DRV_GET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_enable + acl_prop->acl_priority, &ds);
    acl_prop->class_id =    DRV_GET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_label + acl_prop->acl_priority, &ds);
    lkup_type =             DRV_GET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_lkup_type + acl_prop->acl_priority, &ds);
    gport_type =            DRV_GET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_gport_type + acl_prop->acl_priority, &ds);
    use_mapped_vlan =       DRV_GET_FIELD_V(lchip, glb_acl_lkup.table_id, glb_acl_lkup.field_use_pi_vlan + acl_prop->acl_priority, &ds);
    use_wlan =              GetIpePreLookupAclCtl(V, gGlbAcl_0_aclUseCapwapInfo_f + acl_prop->acl_priority,  &ds);

    acl_prop->tcam_lkup_type  = sys_usw_unmap_acl_tcam_lkup_type(lchip, lkup_type);
    if(use_mapped_vlan)
    {
        CTC_SET_FLAG(acl_prop->flag, CTC_ACL_PROP_FLAG_USE_MAPPED_VLAN);
    }
    if(use_wlan)
    {
        CTC_SET_FLAG(acl_prop->flag, CTC_ACL_PROP_FLAG_USE_WLAN);
    }

    if(gport_type == DRV_ENUM(DRV_FLOWPORTTYPE_BITMAP))
    {
        CTC_SET_FLAG(acl_prop->flag, CTC_ACL_PROP_FLAG_USE_PORT_BITMAP);
    }
    else if(gport_type == DRV_ENUM(DRV_FLOWPORTTYPE_LPORT))
    {
        CTC_SET_FLAG(acl_prop->flag, CTC_ACL_PROP_FLAG_USE_LOGIC_PORT);
    }
    else if(gport_type == DRV_ENUM(DRV_FLOWPORTTYPE_METADATA))
    {
        CTC_SET_FLAG(acl_prop->flag, CTC_ACL_PROP_FLAG_USE_METADATA);
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_get_glb_ipmc_property(uint8 lchip, ctc_global_ipmc_property_t* ipmc_prop)
{
    uint32 cmd = 0;
    uint32 value = 0;

    cmd = DRV_IOR(FibEngineLookupCtl_t, FibEngineLookupCtl_l2mcMacIpParallel_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    ipmc_prop->ip_l2mc_mode = value?1:0;

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_set_glb_flow_property(uint8 lchip, ctc_global_flow_property_t* p_flow_prop)
{
    uint32 field_val = 0;
    uint32 cmd = 0;
    IpeFwdCategoryCtl_m ipe_fwd_cid_ctl;

    sal_memset(&ipe_fwd_cid_ctl, 0, sizeof(IpeFwdCategoryCtl_m));

    CTC_MAX_VALUE_CHECK(p_flow_prop->igs_vlan_range_mode, CTC_GLOBAL_VLAN_RANGE_MODE_MAX-1);
    CTC_MAX_VALUE_CHECK(p_flow_prop->egs_vlan_range_mode, CTC_GLOBAL_VLAN_RANGE_MODE_MAX-1);

    if (CTC_GLOBAL_VLAN_RANGE_MODE_SCL == p_flow_prop->igs_vlan_range_mode)
    {
        field_val = 0;
    }
    else if (CTC_GLOBAL_VLAN_RANGE_MODE_ACL == p_flow_prop->igs_vlan_range_mode)
    {
        field_val = 1;
    }
    else if (CTC_GLOBAL_VLAN_RANGE_MODE_SHARE == p_flow_prop->igs_vlan_range_mode)
    {
        field_val = 2;
    }
    cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_vlanRangeMode_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    if (CTC_GLOBAL_VLAN_RANGE_MODE_SCL == p_flow_prop->egs_vlan_range_mode)
    {
        field_val = 0;
    }
    else if (CTC_GLOBAL_VLAN_RANGE_MODE_ACL == p_flow_prop->egs_vlan_range_mode)
    {
        field_val = 1;
    }
    else if (CTC_GLOBAL_VLAN_RANGE_MODE_SHARE == p_flow_prop->egs_vlan_range_mode)
    {
        field_val = 2;
    }
    cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_vlanRangeMode_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_get_glb_flow_property(uint8 lchip, ctc_global_flow_property_t* p_flow_prop)
{
    uint32 field_val = 0;
    uint32 cmd = 0;
    IpeFwdCategoryCtl_m ipe_fwd_cid_ctl;

    sal_memset(&ipe_fwd_cid_ctl, 0, sizeof(IpeFwdCategoryCtl_m));

    cmd = DRV_IOR(IpeUserIdCtl_t, IpeUserIdCtl_vlanRangeMode_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    if (0 == field_val)
    {
        p_flow_prop->igs_vlan_range_mode = CTC_GLOBAL_VLAN_RANGE_MODE_SCL;
    }
    else if (1 == field_val)
    {
        p_flow_prop->igs_vlan_range_mode = CTC_GLOBAL_VLAN_RANGE_MODE_ACL;
    }
    else if (2 == field_val)
    {
        p_flow_prop->igs_vlan_range_mode = CTC_GLOBAL_VLAN_RANGE_MODE_SHARE;
    }

    cmd = DRV_IOR(EpeNextHopCtl_t, EpeNextHopCtl_vlanRangeMode_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    if (0 == field_val)
    {
        p_flow_prop->egs_vlan_range_mode = CTC_GLOBAL_VLAN_RANGE_MODE_SCL;
    }
    else if (1 == field_val)
    {
        p_flow_prop->egs_vlan_range_mode = CTC_GLOBAL_VLAN_RANGE_MODE_ACL;
    }
    else if (2 == field_val)
    {
        p_flow_prop->egs_vlan_range_mode = CTC_GLOBAL_VLAN_RANGE_MODE_SHARE;
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_global_ctl_set_arp_check_en(uint8 lchip, ctc_global_control_type_t type, uint32* value)
{
    uint32 cmd = 0;
    uint32 cmd1 = 0;
    switch (type)
    {
        case CTC_GLOBAL_ARP_MACDA_CHECK_EN:
            cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_arpDestMacCheckEn_f);
            cmd1 = DRV_IOW(IpePreLookupCtl_t, IpePreLookupCtl_arpDestMacCheckEn_f);
            break;
        case CTC_GLOBAL_ARP_MACSA_CHECK_EN:
            cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_arpSrcMacCheckEn_f);
            cmd1 = DRV_IOW(IpePreLookupCtl_t, IpePreLookupCtl_arpSrcMacCheckEn_f);
            break;
        case CTC_GLOBAL_ARP_IP_CHECK_EN:
            cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_arpIpCheckEn_f);
            cmd1 = DRV_IOW(IpePreLookupCtl_t, IpePreLookupCtl_arpIpCheckEn_f);
            break;
        case CTC_GLOBAL_ARP_CHECK_FAIL_TO_CPU:
            cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_arpCheckExceptionEn_f);
            cmd1 = DRV_IOW(IpePreLookupCtl_t, IpePreLookupCtl_arpCheckExceptionEn_f);
            break;
         case CTC_GLOBAL_GRATUITOUS_ARP_TO_CPU:
            cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_gratuitousArpExceptionEn_f);
            cmd1 = DRV_IOW(IpeBridgeCtl_t, IpeBridgeCtl_gratuitousArpExceptionEn_f);
            break;
         case CTC_GLOBAL_ARP_LOCAL_CHECK_EN:
            cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_arpTargetIpCheckEn_f);
            break;
        default:
            return CTC_E_NOT_SUPPORT;
    }
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, value));
    if(0 != cmd1)
    {
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd1, value));
    }

    return CTC_E_NONE;

}


STATIC int32
_sys_usw_global_ctl_get_arp_check_en(uint8 lchip, ctc_global_control_type_t type, uint32* value)
{
    uint32 cmd = 0;

    switch (type)
    {
        case CTC_GLOBAL_ARP_MACDA_CHECK_EN:
            cmd = DRV_IOR(IpeIntfMapperCtl_t, IpeIntfMapperCtl_arpDestMacCheckEn_f);
            break;
        case CTC_GLOBAL_ARP_MACSA_CHECK_EN:
            cmd = DRV_IOR(IpeIntfMapperCtl_t, IpeIntfMapperCtl_arpSrcMacCheckEn_f);
            break;
        case CTC_GLOBAL_ARP_IP_CHECK_EN:
            cmd = DRV_IOR(IpeIntfMapperCtl_t, IpeIntfMapperCtl_arpIpCheckEn_f);
            break;
        case CTC_GLOBAL_ARP_CHECK_FAIL_TO_CPU:
            cmd = DRV_IOR(IpeIntfMapperCtl_t, IpeIntfMapperCtl_arpCheckExceptionEn_f);
            break;
        case CTC_GLOBAL_GRATUITOUS_ARP_TO_CPU:
            cmd = DRV_IOR(IpeIntfMapperCtl_t, IpeIntfMapperCtl_gratuitousArpExceptionEn_f);
            break;
        case CTC_GLOBAL_ARP_LOCAL_CHECK_EN:
            cmd = DRV_IOR(IpeIntfMapperCtl_t, IpeIntfMapperCtl_arpTargetIpCheckEn_f);
            break;
        default:
            return CTC_E_NOT_SUPPORT;
    }
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, value));

    return CTC_E_NONE;

}
/*igmg use fatal exception to cpu by default*/
STATIC int32
_sys_usw_global_ctl_set_igmp_mode(uint8 lchip, ctc_global_control_type_t type, uint32* value)
{

    uint32 cmd = 0;
    uint32 dsfwd_offset = 0;
    uint8 gchip = 0;
    uint16 sub_queue_id = 64;  /*CTC_PKT_CPU_REASON_IGMP_SNOOPING default to 64*/
    uint32 field_val = (*value == CTC_GLOBAL_IGMP_SNOOPING_MODE_2) ?1 :0;
    sys_nh_update_dsfwd_t update_dsfwd_param;
    CTC_MAX_VALUE_CHECK(*value, CTC_GLOBAL_IGMP_SNOOPING_MODE_2);

    cmd = DRV_IOW(IpeRouteCtl_t, IpeRouteCtl_igmpSnoopedMode_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    cmd = DRV_IOW(IpeBridgeCtl_t, IpeBridgeCtl_igmpSnoopedDonotEscape_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    cmd = DRV_IOW(IpeRouteCtl_t, IpeRouteCtl_nonBrgPktIgmpSnoopedExceptionEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    cmd = DRV_IOW(IpeRouteCtl_t, IpeRouteCtl_nonBrgPktIgmpSnoopedDiscardEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));
    /*MODE_0 :igmp will be identified as fatal exception,send fatal exception to CPU--can't do copp & vlan flooding */
    /*MODE_1 :igmp will be identified as fatal exception,must use acl to classify it as normal exception--can do copp */
    /*MODE_2: igmp from vlan if will be identified as normal exception, -- can do vlan flooding & copp
              igmp from phy if/sub if must enable bridge */
    sal_memset(&update_dsfwd_param, 0, sizeof(update_dsfwd_param));
    CTC_ERROR_RETURN(sys_usw_nh_get_fatal_excp_dsnh_offset(lchip, &dsfwd_offset));
    update_dsfwd_param.dsfwd_offset = dsfwd_offset + 12 * 2; /* SYS_FATAL_EXCP_IGMP_SNOOPED_PACKET   = 12 */
    update_dsfwd_param.dest_map = (*value == CTC_GLOBAL_IGMP_SNOOPING_MODE_0) ? SYS_ENCODE_EXCP_DESTMAP(gchip, sub_queue_id) : SYS_ENCODE_DESTMAP(gchip, SYS_RSV_PORT_DROP_ID);
    update_dsfwd_param.dsnh_offset = CTC_PKT_CPU_REASON_BUILD_NHPTR(CTC_PKT_CPU_REASON_IGMP_SNOOPING, 0);
    update_dsfwd_param.critical_packet = 1;
    CTC_ERROR_RETURN(sys_usw_nh_update_dsfwd(lchip, &update_dsfwd_param));
    return CTC_E_NONE;

}
STATIC int32
_sys_usw_global_ctl_get_igmp_mode(uint8 lchip, ctc_global_control_type_t type, uint32* value)
{
   uint32 cmd = 0;
   uint32 field_val = 0;
   uint32 dsfwd_offset = 0;
   DsFwd_m dsfwd;
   DsFwdHalf_m dsfwd_half;
   uint32 dest_map = 0;

   cmd = DRV_IOR(IpeRouteCtl_t, IpeRouteCtl_igmpSnoopedMode_f);
   CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

   CTC_ERROR_RETURN(sys_usw_nh_get_fatal_excp_dsnh_offset(lchip, &dsfwd_offset));
   /* SYS_FATAL_EXCP_IGMP_SNOOPED_PACKET   = 12 */
   dsfwd_offset = dsfwd_offset + 12 * 2;
   cmd = DRV_IOR(DsFwd_t, DRV_ENTRY_FLAG);
   DRV_IOCTL(lchip, dsfwd_offset / 2, cmd, &dsfwd);
   if (dsfwd_offset % 2 == 0)
   {
       GetDsFwdDualHalf(A, g_0_dsFwdHalf_f,   &dsfwd,   &dsfwd_half);
   }
   else
   {
       GetDsFwdDualHalf(A, g_1_dsFwdHalf_f,   &dsfwd,   &dsfwd_half);
   }
   dest_map = GetDsFwdHalf(V, destMap_f, &dsfwd_half);
   if (dest_map >> 16 && (field_val == 0) )  /*SYS_ENCODE_EXCP_DESTMAP*/
   {  /*to cpu*/
       *value  = CTC_GLOBAL_IGMP_SNOOPING_MODE_0;
   }
   else if(field_val == 1)
   {
       *value  = CTC_GLOBAL_IGMP_SNOOPING_MODE_2;
   }
   else
   {
       *value  = CTC_GLOBAL_IGMP_SNOOPING_MODE_1;
   }

    return CTC_E_NONE;

}

STATIC int32
_sys_usw_set_dump_db(uint8 lchip, ctc_global_dump_db_t* p_dump_param)
{
    int32 ret = CTC_E_NONE;
    sal_file_t p_file = NULL;
    char cfg_file[300] = {0};
    char line_buf[121] = {0};
    uint16 str_len = 0;
    uint8 feature = 0;
    uint8 pp_id = 0;

    CTC_PTR_VALID_CHECK(p_dump_param);
    LCHIP_CHECK(lchip);
    if(sal_strlen(p_dump_param->file) != 0)
    {
        sal_sprintf(cfg_file, "%s%s", p_dump_param->file, ".txt");
        p_file = sal_fopen(cfg_file, "wb+");

        if (NULL == p_file)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_ERROR," Store file: %s failed!\n\n", cfg_file);
            goto CTC_DUMP_DB_END;
        }
    }

    str_len += sal_sprintf(line_buf + str_len, "%s", "---------------------------------------------------**** lchip: ");
    str_len += sal_sprintf(line_buf + str_len, "%d", lchip);
    str_len += sal_sprintf(line_buf + str_len, "%s", " ****---------------------------------------------------");
    SYS_DUMP_DB_LOG(p_file, "%s\n", line_buf);
    SYS_DUMP_DB_LOG(p_file, "%s\n", "************************************************* CTC SDK DEBUG DUMP ***************************************************");
    SYS_DUMP_DB_LOG(p_file, "%s %s\n", "SDK Version       :", CTC_SDK_VERSION_STR);
    SYS_DUMP_DB_LOG(p_file, "%s %s\n", "SDK Release Date  :", CTC_SDK_RELEASE_DATE);
    SYS_DUMP_DB_LOG(p_file, "%s %s\n", "SDK Copyright Time:", CTC_SDK_COPYRIGHT_TIME);
    SYS_DUMP_DB_LOG(p_file, "%s %s\n", "Chip Series       :",g_ctcs_api_en ? ctcs_get_chip_name(lchip):ctc_get_chip_name());
    SYS_DUMP_DB_LOG(p_file, "%s %s %s\n", "Compile time      :",__DATE__,__TIME__);
    SYS_DUMP_DB_LOG(p_file, "%s\n", "************************************************* CTC SDK DEBUG DUMP ***************************************************");
    for (feature = 0; feature < CTC_FEATURE_MAX; feature++)
    {
        if (CTC_BMP_ISSET(p_dump_param->bit_map, feature) && p_usw_chip_master[lchip]->dump_cb[feature])
        {
            SYS_FEATURE_PP_LOOP_START(lchip, feature, pp_id);
            if (DRV_FROM_AT(lchip) && MCHIP_FEATURE_PP_EN(lchip, feature))
            {
                str_len = 0;
                str_len += sal_sprintf(line_buf + str_len, "%s", "===================================================#### PP: ");
                str_len += sal_sprintf(line_buf + str_len, "%d", pp_id);
                str_len += sal_sprintf(line_buf + str_len, "%s", " ####===================================================");
                SYS_DUMP_DB_LOG(p_file, "%s\n", line_buf);
            }
            CTC_ERROR_GOTO(p_usw_chip_master[lchip]->dump_cb[feature](lchip+pp_id, p_file, p_dump_param),ret,CTC_DUMP_DB_END);
            SYS_FEATURE_PP_LOOP_END(pp_id);
        }
    }

CTC_DUMP_DB_END:
    if (NULL != p_file)
    {
        sal_fclose(p_file);
    }
    return CTC_E_NONE;
}

int32
_sys_usw_set_warmboot_sync(uint8 lchip)
{
    uint8 i, pp_id = 0;
    uint8 mod = 0;
    /*sync up all data to memory */
    //CTC_ERROR_RETURN(p_usw_register_master[lchip]->wb_sync_cb[CTC_FEATURE_SC_OAM](lchip,0));
    //return 0;
    for (i = 0; i < CTC_FEATURE_MAX; i++)
    {
        mod = i;
        if (CTC_FEATURE_OVERLAY == i)
        {
            mod = CTC_FEATURE_SCL;
        }
        SYS_FEATURE_PP_LOOP_START(lchip, mod, pp_id)
        if (p_usw_register_master[lchip]->wb_sync_cb[i])
        {
            CTC_ERROR_RETURN(p_usw_register_master[lchip]->wb_sync_cb[i](lchip+pp_id,0));
        }
        SYS_FEATURE_PP_LOOP_END(pp_id)
    }

    return CTC_E_NONE;
}
#if 0
STATIC uint32
_sys_usw_register_hash_make_cethertype(sys_register_cethertype_t* pa)
{
    uint32 size = sizeof(uint16);
    return ctc_hash_caculate(size, &pa->ether_type);
}

/*acl cethertype spool*/
STATIC bool
_sys_usw_register_hash_compare_cethertype(sys_register_cethertype_t* pa0,
                                           sys_register_cethertype_t* pa1)
{
    if (!pa0 || !pa1)
    {
        return FALSE;
    }

    if (pa0->ether_type == pa1->ether_type)
    {
        return TRUE;
    }

    return FALSE;
}

STATIC int32
_sys_usw_register_build_cethertype_index(sys_register_cethertype_t* pa, uint8* p_lchip)
{
    sys_usw_opf_t opf;
    uint32               value_32 = 0;

    sal_memset(&opf, 0, sizeof(sys_usw_opf_t));

    opf.pool_type  = p_usw_register_master[*p_lchip]->opf_type_cethertype;
    if (CTC_WB_STATUS(*p_lchip) == CTC_WB_STATUS_RELOADING)
    {
        CTC_ERROR_RETURN(sys_usw_opf_alloc_offset_from_position(*p_lchip, &opf, 1, pa->cethertype_index));
    }
    else
    {
        CTC_ERROR_RETURN(sys_usw_opf_alloc_offset(*p_lchip, &opf, 1, &value_32));
        pa->cethertype_index = value_32 & 0x3F;
    }
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_register_free_cethertype_index(sys_register_cethertype_t* pa, uint8* p_lchip)
{
    sys_usw_opf_t opf;

    sal_memset(&opf, 0, sizeof(sys_usw_opf_t));

    opf.pool_type = p_usw_register_master[*p_lchip]->opf_type_cethertype;

    CTC_ERROR_RETURN(sys_usw_opf_free_offset(*p_lchip, &opf, 1, pa->cethertype_index));

    return CTC_E_NONE;
}
#endif
int32
_sys_usw_register_cethertype_spool_init(uint8 lchip)
{
    uint32 cethertype_num = 0;
    ctc_spool_t spool;
    sys_usw_opf_t opf;
    uint8 opf_type = 0;

    sal_memset(&opf, 0, sizeof(opf));
    CTC_ERROR_RETURN(sys_usw_ftm_query_table_entry_num(lchip, EtherTypeCompressCam_t, &cethertype_num));
    if(cethertype_num)
    {
        CTC_ERROR_RETURN(sys_usw_opf_init(lchip, &opf_type, 1, "opf-register-cethertype"));
        p_usw_register_master[lchip]->opf_type_cethertype = opf_type;
        opf.pool_index = 0;
        opf.pool_type  = p_usw_register_master[lchip]->opf_type_cethertype;
        CTC_ERROR_RETURN(sys_usw_opf_init_offset(lchip, &opf, 0, cethertype_num));
    }

    /*spool for cethertype*/
    sal_memset(&spool, 0, sizeof(ctc_spool_t));
    spool.lchip = lchip;
    spool.block_num = 1;
    spool.block_size = cethertype_num;
    spool.max_count = cethertype_num;
    spool.user_data_size = sizeof(sys_register_cethertype_t);
    spool.desc = "opf-register-cethertype";
    spool.key_size = CTC_OFFSET_OF(sys_register_cethertype_t, calc_len);
    spool.min_index = 0;
    spool.max_index = cethertype_num - 1;

    p_usw_register_master[lchip]->cethertype_spool = ctc_spool_create(&spool);

    return CTC_E_NONE;
}

/*Truncation profile init*/
int32
_sys_usw_register_tcat_prof_init(uint8 lchip)
{
    uint8 loop = 0;
    uint8 shift_hw = 0;
    uint8 len_hw = 0;
    uint32 cmd = 0;
    DsTruncationProfile_m truncation_prof;
    uint16 length[SYS_TRUNCATION_PROFILE_MAX] =   {0,    64,   96,  128,
                                                       192,  256,  320, 384,
                                                       512,  640,  768, 896,
                                                       1024, 1280, 1536, 2040};

    uint16 tcat_length[SYS_TRUNCATION_PROFILE_MAX] = {1024,    64,   96,  128,
                                                       160, 192, 224, 256,
                                                       288, 320, 384, 512,
                                                       640,  768, 896, 960};

    length[SYS_TRUNCATION_PROFILE_USER_END] = MCHIP_CAP(SYS_CAP_PKT_TRUNCATED_LEN);
    for (loop = 0; loop < SYS_TRUNCATION_PROFILE_MAX; loop++)
    {
        CTC_ERROR_RETURN(_sys_usw_map_truncation_len_user_to_hw( \
            ((DRV_IS_TMM(lchip) && (SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_C)) || DRV_IS_TMG(lchip))?tcat_length[loop]:length[loop], &len_hw, &shift_hw));
        cmd = DRV_IOR(DsTruncationProfile_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, loop, cmd, &truncation_prof));
        SetDsTruncationProfile(V, lengthShift_f, &truncation_prof, shift_hw);
        SetDsTruncationProfile(V, length_f, &truncation_prof, len_hw);
        cmd = DRV_IOW(DsTruncationProfile_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, loop, cmd, &truncation_prof));
    }

    return CTC_E_NONE;
}

int32
sys_usw_register_wb_sync(uint8 lchip, uint32 app_id)
{
    int32 ret = CTC_E_NONE;
    sys_wb_register_master_t* p_wb_register_master = NULL;
    ctc_wb_data_t wb_data = {0};

    /*sync up master*/
    CTC_WB_ALLOC_BUFFER(&wb_data.buffer);
    SYS_USW_REGISTER_LOCK(lchip);

    if (app_id == 0 || CTC_WB_SUBID(app_id) == SYS_WB_APPID_REGISTER_SUBID_MASTER)
    {

        CTC_WB_INIT_DATA_T((&wb_data), sys_wb_register_master_t, CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MASTER);

        p_wb_register_master = (sys_wb_register_master_t*)wb_data.buffer;
        p_wb_register_master->lchip = lchip;
        p_wb_register_master->version = SYS_WB_VERSION_REGISTER;
        p_wb_register_master->oam_coexist_mode = p_usw_register_master[lchip]->tpoam_vpws_coexist;
        p_wb_register_master->derive_mode = p_usw_register_master[lchip]->derive_mode;
        p_wb_register_master->logic_threshold = p_usw_register_master[lchip]->logic_rep_threshold;
        p_wb_register_master->wb_keep_knet = p_usw_register_master[lchip]->wb_keep_knet;
        p_wb_register_master->station_move_mode = p_usw_register_master[lchip]->station_move_mode;
        wb_data.valid_cnt = 1;
        CTC_ERROR_GOTO(ctc_wb_add_entry(&wb_data), ret, done);
        CTC_WB_SYNC_END_DATA(CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MASTER);
    }
    done:
    SYS_USW_REGISTER_UNLOCK(lchip);
    CTC_WB_FREE_BUFFER(wb_data.buffer);

    return ret;
}

int32 sys_usw_register_wb_restore(uint8 lchip)
{
    int32 ret = CTC_E_NONE;
    sys_wb_register_master_t wb_register_master = {0};
    ctc_wb_query_t    wb_query;

    CTC_WB_ALLOC_BUFFER(&wb_query.buffer);

    CTC_WB_INIT_QUERY_T((&wb_query),sys_wb_register_master_t, CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MASTER);

    CTC_ERROR_GOTO(ctc_wb_query_entry(&wb_query), ret, done);

    if (wb_query.valid_cnt != 1 || wb_query.is_end != 1)
    {
        CTC_WB_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "query register master error! valid_cnt: %d, is_end: %d.\n", wb_query.valid_cnt, wb_query.is_end);
        ret = CTC_E_NONE;
        goto done;
    }

    sal_memcpy((uint8*)&wb_register_master, (uint8*)wb_query.buffer, wb_query.key_len + wb_query.data_len);

    if (CTC_WB_VERSION_CHECK(SYS_WB_VERSION_REGISTER, wb_register_master.version))
    {
        ret = CTC_E_VERSION_MISMATCH;
        goto done;
    }
    p_usw_register_master[lchip]->tpoam_vpws_coexist = wb_register_master.oam_coexist_mode;
    p_usw_register_master[lchip]->derive_mode = wb_register_master.derive_mode;
    p_usw_register_master[lchip]->logic_rep_threshold = wb_register_master.logic_threshold;
    p_usw_register_master[lchip]->wb_keep_knet = wb_register_master.wb_keep_knet;
    p_usw_register_master[lchip]->station_move_mode = wb_register_master.station_move_mode;

    if (DRV_FROM_TMM(lchip))
    {
        uint32 cmd = 0;
        uint32 field_val = 0;
        cmd = DRV_IOR(EpePktProcCtl_t, EpePktProcCtl_sr6ReducedMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        p_usw_register_master[lchip]->sid_edit_mode = field_val;
    }
done:
   CTC_WB_FREE_BUFFER(wb_query.buffer);

   return ret;
}

STATIC int32
_sys_usw_register_wb_init(uint8 lchip)
{
    ctc_wb_appid_t  appid;
    sal_memset(&appid, 0, sizeof(appid));

    appid.app_id = lchip << 16 | CTC_WB_APPID(CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MASTER) ;
    appid.entry_num = 1;
    appid.entry_size  = sizeof(sys_wb_register_master_t);
    appid.rt_en = 0;
   ctc_wb_add_appid(lchip, &appid);

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_register_init_module(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 value = 1;
    uint32 idx = 0;
    uint32 loop = 0;
    ds_t   ds;
#ifndef EMULATION_ENV
    ProgramAclTcamMiscCtl_m prg_ctl;
    UserIdHashTcamMiscCtl_m ht_ctl;
    UserIdTcamMiscCtl_m t_ctl;
#endif

    if(DRV_FROM_AT(lchip))
    {
        /*dot1ae*/
        value = MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_DOT1AE) ? 1: 0;
        cmd = DRV_IOR(CtcDpRxCtlClockEn_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetCtcDpRxCtlClockEn(V, enClkXSecDec_f, ds, value);
        cmd = DRV_IOW(CtcDpRxCtlClockEn_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    
        cmd = DRV_IOR(CtcDpTxCtlClockEn_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetCtcDpTxCtlClockEn(V, enClkXSecEnc_f, ds, value);
        cmd = DRV_IOW(CtcDpTxCtlClockEn_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        
        /*ipfix*/
        value = MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_IPFIX) ? 1: 0;
        cmd = DRV_IOR(CtcEpeTxModuleEnable_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetCtcEpeTxModuleEnable(V, enClkIpfixHash_f, ds, value);
        SetCtcEpeTxModuleEnable(V, enClkFlowAcc_f, ds, value);
        cmd = DRV_IOW(CtcEpeTxModuleEnable_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

        cmd = DRV_IOR(CtcIpeTxClkEn_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetCtcIpeTxClkEn(V, enClkFlowAcc_f, ds, value);
        SetCtcIpeTxClkEn(V, enClkIpfixHash_f, ds, value);
        cmd = DRV_IOW(CtcIpeTxClkEn_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        
        /*oam*/
        value = (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_OAM) || MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_NPM)) ? 1: 0;
        cmd = DRV_IOR(CtcMiscCtlModuleEn_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetCtcMiscCtlModuleEn(V, enClkOamEngine_f, ds, value);
        cmd = DRV_IOW(CtcMiscCtlModuleEn_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

        /*default to disable ecpu all clk*/
        cmd = DRV_IOR(EcpuSupEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetEcpuSupEnClk(V, enClkGlobalAxi_f, ds, 0);
        cmd = DRV_IOW(EcpuSupEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

        cmd = DRV_IOR(EcpuDmaEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetEcpuDmaEnClk(V, cfgEcpu0DmaEnClk_f, ds, 0);
        SetEcpuDmaEnClk(V, cfgEcpu1DmaEnClk_f, ds, 0);
        cmd = DRV_IOW(EcpuDmaEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

        for(loop=0; loop<MCHIP_CAP(SYS_CAP_EUNIT_NUM); loop++)
        {
            cmd = DRV_IOR(Ecpu00EnClk_t+(loop&0x3), DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            SetEcpu00EnClk(V, cfgEcpuCoreEnClk_f, ds, 0);
            SetEcpu00EnClk(V, cfgEcpuIntfEnClk_f, ds, 0);
            cmd = DRV_IOW(Ecpu00EnClk_t+(loop&0x3), DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        }

        return CTC_E_NONE;
    }
    
    /*1. set init*/
    /*acl*/
    if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_ACL))
    {
        cmd = DRV_IOW(EgressAclTcamInit_t, EgressAclTcamInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(FlowHashInit_t, FlowHashInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(IpeAclInit_t, IpeAclInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(ProgramAclLtidTcamInit_t, ProgramAclLtidTcamInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(ProgramAclTcamInit_t, ProgramAclTcamInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        if (DRV_IS_TMM(lchip) && CTC_WB_STATUS(lchip) != CTC_WB_STATUS_RELOADING)
        {
            drv_ds_t ds_data;

            /* for rtl not init bug */
            sal_memset(&ds_data, 0, sizeof(ds_data));
            cmd = DRV_IOW(ProgramAclTcamMem_t, DRV_ENTRY_FLAG);
            for (idx = 0; idx < TABLE_MAX_INDEX(lchip, ProgramAclTcamMem_t); idx++)
            {
                DRV_IOCTL(lchip, idx, cmd, &ds_data);
            }

            cmd = DRV_IOW(DsLtidSelectTcamMem_t, DRV_ENTRY_FLAG);
            for (idx = 0; idx < TABLE_MAX_INDEX(lchip, DsLtidSelectTcamMem_t); idx++)
            {
                DRV_IOCTL(lchip, idx, cmd, &ds_data);
            }
        }
    }
    /*ipmc*/
    cmd = DRV_IOW(FibHashHost1Init_t, FibHashHost1Init_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    /*ipuc*/
    cmd = DRV_IOW(FibHashHost0Init_t, FibHashHost0Init_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(LpmTcamInit_t, LpmTcamInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    /*fdb*/
    cmd = DRV_IOW(DynamicFibKeyInit_t, DynamicFibKeyInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(FibAccInit_t, FibAccInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(FibEngineInit_t, FibEngineInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    /*learning_aging*/
    cmd = DRV_IOW(DsAgingInit_t, DsAgingInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    /*linkagg	*/
    cmd = DRV_IOW(LinkAggInit_t, LinkAggInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    /*nexthop*/
    cmd = DRV_IOW(DynamicEditInit_t, DynamicEditInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(EcmpDlbInit_t, EcmpDlbInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    /*parser	*/
    for (idx = 0; idx < 3; idx++)
    {
        cmd = DRV_IOW(ParserInit_t, ParserInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, idx, cmd, &value));
    }
    /*qos*/
    cmd = DRV_IOW(CoppEpeInit_t, CoppEpeInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(CoppIpeInit_t, CoppIpeInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(PolicingEpeInit_t, PolicingEpeInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(PolicingIpeInit_t, PolicingIpeInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(SvcPolicingInit_t, SvcPolicingInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    /*scl */
    cmd = DRV_IOW(EgrSclHashInit_t, EgrSclHashInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(UserIdHashInit_t, UserIdHashInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(UserIdHashTcamInit_t, UserIdHashTcamInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(UserIdTcamInit_t, UserIdTcamInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    /*security*/
    cmd = DRV_IOW(StormCtlInit_t, StormCtlInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    /*app-vlan-port*/
    cmd = DRV_IOW(GemPortHashInit_t, GemPortHashInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    for (idx = 0; idx < MCHIP_CAP(SYS_CAP_DP_MAX_NUM); idx++)
    {
        /*dot1ae*/
        if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_DOT1AE))
        {
            cmd = DRV_IOW(MacSecDecInit_t, MacSecDecInit_init_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, idx, cmd, &value));

            cmd = DRV_IOW(MacSecEncInit_t, MacSecEncInit_init_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, idx, cmd, &value));
        }
        /*flexe*/
        if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_FLEXE))
        {
            cmd = DRV_IOW(FlexeMgrInit_t, FlexeMgrInit_init_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, idx, cmd, &value));
        }
    }
    /*efd*/
    if(!DRV_IS_TMG(lchip))
    {
    cmd = DRV_IOW(EfdInit_t, EfdInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }
    /*ipfix*/
    if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_IPFIX))
    {
        cmd = DRV_IOW(FlowAccAdInit_t, FlowAccAdInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(FlowAccEpeInit_t, FlowAccEpeInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(FlowAccIpeInit_t, FlowAccIpeInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(IpfixHashInit_t, IpfixHashInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }
    /*mpls*/

    cmd = DRV_IOW(MplsHashInit_t, MplsHashInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    /*npm*/
    if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_NPM))
    {
        cmd = DRV_IOW(OamAutoGenPktInit_t, OamAutoGenPktInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }
    /*oam*/
    if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_OAM))
    {
        cmd = DRV_IOW(LmStatsInit_t, LmStatsInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(OamFwdInit_t, OamFwdInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(OamHashInit_t, OamHashInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(OamProcInit_t, OamProcInit_init_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }
    /*sc-oam*/
    cmd = DRV_IOW(SpnOamInit_t, SpnOamInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    /*stats*/
    cmd = DRV_IOW(GlobalStatsInit_t, GlobalStatsInit_init_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    #ifdef EMULATION_ENV
    sal_task_sleep(5000);
    #else
    /*2. check init done */
    sal_task_sleep(1);
    if (0 == SDK_WORK_PLATFORM)
    {
        /*acl*/
        cmd = DRV_IOR(EgressAclTcamInitDone_t, EgressAclTcamInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EgressAclTcamInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(FlowHashInitDone_t, FlowHashInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlowHashInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(IpeAclInitDone_t, IpeAclInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [IpeAclInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(ProgramAclLtidTcamInitDone_t, ProgramAclLtidTcamInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [ProgramAclLtidTcamInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(ProgramAclTcamInitDone_t, ProgramAclTcamInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [ProgramAclTcamInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        /*ipmc*/
        cmd = DRV_IOR(FibHashHost1InitDone_t, FibHashHost1InitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FibHashHost1InitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        /*ipuc*/
        cmd = DRV_IOR(FibHashHost0InitDone_t, FibHashHost0InitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FibHashHost0InitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(LpmTcamInitDone_t, LpmTcamInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [LpmTcamInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        /*fdb*/
        cmd = DRV_IOR(DynamicFibKeyInitDone_t, DynamicFibKeyInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [DynamicFibKeyInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(FibAccInitDone_t, FibAccInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FibAccInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(FibEngineInitDone_t, FibEngineInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FibEngineInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        /*learning_aging*/
        cmd = DRV_IOR(DsAgingInitDone_t, DsAgingInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [DsAgingInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        /*linkagg*/
        cmd = DRV_IOR(LinkAggInitDone_t, LinkAggInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [LinkAggInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        /*nexthop*/
        cmd = DRV_IOR(DynamicEditInitDone_t, DynamicEditInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [DynamicEditInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(EcmpDlbInitDone_t, EcmpDlbInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EcmpDlbInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        /*paser*/
        for (idx = 0; idx < 3; idx++)
        {
            cmd = DRV_IOR(ParserInitDone_t, ParserInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, idx, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [ParserInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
        }
        /*qos*/
        cmd = DRV_IOR(CoppEpeInitDone_t, CoppEpeInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [CoppEpeInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(CoppIpeInitDone_t, CoppIpeInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [CoppIpeInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(PolicingEpeInitDone_t, PolicingEpeInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [PolicingEpeInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(PolicingIpeInitDone_t, PolicingIpeInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [PolicingIpeInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(SvcPolicingInitDone_t, SvcPolicingInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [SvcPolicingInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        /*scl*/
        cmd = DRV_IOR(EgrSclHashInitDone_t, EgrSclHashInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EgrSclHashInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(UserIdHashInitDone_t, UserIdHashInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [UserIdHashInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(UserIdHashTcamInitDone_t, UserIdHashTcamInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [UserIdHashTcamInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        cmd = DRV_IOR(UserIdTcamInitDone_t, UserIdTcamInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [UserIdTcamInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        /*security*/
        cmd = DRV_IOR(StormCtlInitDone_t, StormCtlInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [StormCtlInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }

        /*app-vlan-port*/
        cmd = DRV_IOR(GemPortHashInitDone_t, GemPortHashInitDone_initDone_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!value)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [GemPortHashInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }

        for (idx = 0; idx < MCHIP_CAP(SYS_CAP_DP_MAX_NUM); idx++)
        {
            /*dot1ae*/
            if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_DOT1AE))
            {
                cmd = DRV_IOR(MacSecDecInitDone_t, MacSecDecInitDone_initDone_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, idx, cmd, &value));
                if (!value)
                {
                    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [MacSecDecInitDone.initDone] Feature not initialized \n");
                    return CTC_E_NOT_INIT;
                }
                cmd = DRV_IOR(MacSecEncInitDone_t, MacSecEncInitDone_initDone_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, idx, cmd, &value));
                if (!value)
                {
                    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [MacSecEncInitDone.initDone] Feature not initialized \n");
                    return CTC_E_NOT_INIT;
                }
            }
            /*flexe*/
            if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_FLEXE))
            {
                cmd = DRV_IOR(FlexeMgrInitDone_t, FlexeMgrInitDone_initDone_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, idx, cmd, &value));
                if (!value)
                {
                    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlexeMgrInitDone.initDone] Feature not initialized \n");
                    return CTC_E_NOT_INIT;
                }
            }
        }
        /*efd*/
        if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_EFD))
        {
            cmd = DRV_IOR(EfdInitDone_t, EfdInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EfdInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
        }
        /*ipfix*/
        if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_IPFIX))
        {
            cmd = DRV_IOR(FlowAccAdInitDone_t, FlowAccAdInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlowAccAdInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
            cmd = DRV_IOR(FlowAccEpeInitDone_t, FlowAccEpeInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlowAccEpeInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
            cmd = DRV_IOR(FlowAccIpeInitDone_t, FlowAccIpeInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlowAccIpeInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
            cmd = DRV_IOR(IpfixHashInitDone_t, IpfixHashInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [IpfixHashInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
        }
        /*mpls*/
        if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_MPLS))
        {
            cmd = DRV_IOR(MplsHashInitDone_t, MplsHashInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [MplsHashInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
        }
        /*npm*/
        if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_NPM))
        {
            cmd = DRV_IOR(OamAutoGenPktInitDone_t, OamAutoGenPktInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [OamAutoGenPktInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
        }
        /*oam*/
        if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_OAM))
        {
            cmd = DRV_IOR(LmStatsInitDone_t, LmStatsInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [LmStatsInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
            cmd = DRV_IOR(OamFwdInitDone_t, OamFwdInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [OamFwdInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
            cmd = DRV_IOR(OamHashInitDone_t, OamHashInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [OamHashInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
            cmd = DRV_IOR(OamProcInitDone_t, OamProcInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [OamProcInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
        }
        /*sc-oam*/
        if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_SC_OAM))
        {
            cmd = DRV_IOR(SpnOamInitDone_t, SpnOamInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [SpnOamInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
        }
        /*stats*/
        if (MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_STATS))
        {
            cmd = DRV_IOR(GlobalStatsInitDone_t, GlobalStatsInitDone_initDone_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            if (!value)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [GlobalStatsInitDone.initDone] Feature not initialized \n");
                return CTC_E_NOT_INIT;
            }
        }
        /*init done additional cfg*/

        /*ProgramAclTcamMiscCtl.aclCpuStallDlySel write 11*/
        cmd = DRV_IOR(ProgramAclTcamMiscCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &prg_ctl));
        value = 11;
        DRV_IOW_FIELD(lchip, ProgramAclTcamMiscCtl_t, ProgramAclTcamMiscCtl_aclCpuStallDlySel_f, &value, &prg_ctl);
        cmd = DRV_IOW(ProgramAclTcamMiscCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &prg_ctl));

        /*UserIdHashTcamMiscCtl.cpuStallDlySel write 0x5*/
        cmd = DRV_IOR(UserIdHashTcamMiscCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ht_ctl));
        value = 0x5;
        DRV_IOW_FIELD(lchip, UserIdHashTcamMiscCtl_t, UserIdHashTcamMiscCtl_cpuStallDlySel_f, &value, &ht_ctl);
        cmd = DRV_IOW(UserIdHashTcamMiscCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ht_ctl));

        /*UserIdTcamMiscCtl.cpuStallDlySel write 0x4*/
        cmd = DRV_IOR(UserIdTcamMiscCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &t_ctl));
        value = 0x4;
        DRV_IOW_FIELD(lchip, UserIdTcamMiscCtl_t, UserIdTcamMiscCtl_cpuStallDlySel_f, &value, &t_ctl);
        cmd = DRV_IOW(UserIdTcamMiscCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &t_ctl));
    }
    #endif

    /*3. set clock enable  */
#ifndef EMULATION_ENV
    value = MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_DOT1AE) ? 1: 0;
    //for (idx = 0; idx < MCHIP_CAP(SYS_CAP_DP_MAX_NUM); idx++)
    //{AT_TODO, CtcDpTxCtlClockEn contains only 1 entry in spec version 24
        cmd = DRV_IOR(CtcDpTxCtlClockEn_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetCtcDpTxCtlClockEn(V, enClkMacSecEnc_f, ds, value);
        cmd = DRV_IOW(CtcDpTxCtlClockEn_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

        cmd = DRV_IOR(CtcDpRxCtlClockEn_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetCtcDpRxCtlClockEn(V, enClkMacSecDec_f, ds, value);
        cmd = DRV_IOW(CtcDpRxCtlClockEn_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    //}
#endif
    value = MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_IPFIX) ? 1: 0;
    cmd = DRV_IOR(CtcIpeTxClkEn_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetCtcIpeTxClkEn(V, enClkFlowAcc_f, ds, 1);
    SetCtcIpeTxClkEn(V, enClkIpfixHash_f, ds, value);
    cmd = DRV_IOW(CtcIpeTxClkEn_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(CtcMiscCtlClkEn_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    /*HMAC default disable*/
    SetCtcMiscCtlClkEn(V, enClkHMacEngine_f, ds, 0);
    SetCtcMiscCtlClkEn(V, enClkOamEngine_f, ds, 1);
    SetCtcMiscCtlClkEn(V, enClkSpnOam_f, ds, 1);
    cmd = DRV_IOW(CtcMiscCtlClkEn_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    value = MCHIP_FEATURE_INIT(lchip, CTC_FEATURE_FLEXE) ? 1: 0;
    for (idx = 0; idx < MCHIP_CAP(SYS_CAP_DP_MAX_NUM); idx++)
    {
        cmd = DRV_IOR(CtcFlexeCrossCtlEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, idx, cmd, &ds));
        SetCtcFlexeCrossCtlEnClk(V, enClkMcu_f, ds, value);
        SetCtcFlexeCrossCtlEnClk(V, enClkMcuIntf_f, ds, value);
        SetCtcFlexeCrossCtlEnClk(V, enClkFlexeCross_f, ds, value);
        SetCtcFlexeCrossCtlEnClk(V, enClkFlexeCrossReg_f, ds, value);
        cmd = DRV_IOW(CtcFlexeCrossCtlEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, idx, cmd, &ds));
        cmd = DRV_IOR(CtcFlexeShimCtlEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, idx, cmd, &ds));
        SetCtcFlexeShimCtlEnClk(V, enClkFlexeShim_f, ds, value);
        SetCtcFlexeShimCtlEnClk(V, enClkFlexeShimReg_f, ds, value);
        SetCtcFlexeShimCtlEnClk(V, enClkFlexeMgr_f, ds, value);
        cmd = DRV_IOW(CtcFlexeShimCtlEnClk_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, idx, cmd, &ds));
    }

    /*4. set tcam valid bit clear reset*/
    cmd = DRV_IOR(EgessAclTcamBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetEgessAclTcamBitReset(V, tcamValidBitReset_f, ds, 1);
    cmd = DRV_IOW(EgessAclTcamBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetEgessAclTcamBitReset(V, tcamValidBitReset_f, ds, 0);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(EgrSclHashTcamValidBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetEgrSclHashTcamValidBitReset(V, tcam0ValidBitReset_f, ds, 1);
    SetEgrSclHashTcamValidBitReset(V, tcam1ValidBitReset_f, ds, 1);
    cmd = DRV_IOW(EgrSclHashTcamValidBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetEgrSclHashTcamValidBitReset(V, tcam0ValidBitReset_f, ds, 0);
    SetEgrSclHashTcamValidBitReset(V, tcam1ValidBitReset_f, ds, 0);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(IpeAclTcamValidBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetIpeAclTcamValidBitReset(V, tcamValidBitReset_f, ds, 1);
    cmd = DRV_IOW(IpeAclTcamValidBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetIpeAclTcamValidBitReset(V, tcamValidBitReset_f, ds, 0);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(IpeHdrAdjRouterMacTcamValidBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetIpeHdrAdjRouterMacTcamValidBitReset(V, tcamValidBitReset_f, ds, 1);
    cmd = DRV_IOW(IpeHdrAdjRouterMacTcamValidBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetIpeHdrAdjRouterMacTcamValidBitReset(V, tcamValidBitReset_f, ds, 0);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(IpeHdrAdjUdfTcamValidBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetIpeHdrAdjUdfTcamValidBitReset(V, udfTcamValidBitReset_f, ds, 1);
    cmd = DRV_IOW(IpeHdrAdjUdfTcamValidBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetIpeHdrAdjUdfTcamValidBitReset(V, udfTcamValidBitReset_f, ds, 0);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(LpmTcamTcamVaidBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetLpmTcamTcamVaidBitReset(V, tcamValidBitReset_f, ds, 1);
    cmd = DRV_IOW(LpmTcamTcamVaidBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetLpmTcamTcamVaidBitReset(V, tcamValidBitReset_f, ds, 0);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(ProgramAclLtidTcamMiscCtl_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetProgramAclLtidTcamMiscCtl(V, ltidTcamValidBitReset_f, ds, 1);
    cmd = DRV_IOW(ProgramAclLtidTcamMiscCtl_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetProgramAclLtidTcamMiscCtl(V, ltidTcamValidBitReset_f, ds, 0);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(UserIdHashTcamBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetUserIdHashTcamBitReset(V, tcam0ValidBitReset_f, ds, 1);
    SetUserIdHashTcamBitReset(V, tcam1ValidBitReset_f, ds, 1);
    cmd = DRV_IOW(UserIdHashTcamBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetUserIdHashTcamBitReset(V, tcam0ValidBitReset_f, ds, 0);
    SetUserIdHashTcamBitReset(V, tcam1ValidBitReset_f, ds, 0);
    cmd = DRV_IOW(UserIdHashTcamBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(UserIdTcamBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetUserIdTcamBitReset(V, tcam0ValidBitReset_f, ds, 1);
    SetUserIdTcamBitReset(V, tcam1ValidBitReset_f, ds, 1);
    cmd = DRV_IOW(UserIdTcamBitReset_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetUserIdTcamBitReset(V, tcam0ValidBitReset_f, ds, 0);
    SetUserIdTcamBitReset(V, tcam1ValidBitReset_f, ds, 0);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));


    cmd = DRV_IOR(ProgramAclTcamMiscCtl_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetProgramAclTcamMiscCtl(V, aclTcamValidBitReset_f, ds, 0xffff);
    cmd = DRV_IOW(ProgramAclTcamMiscCtl_t,DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetProgramAclTcamMiscCtl(V, aclTcamValidBitReset_f, ds, 0);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    return CTC_E_NONE;
}
STATIC int32
_sys_usw_register_init_l3(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 cmd1 = 0;
    uint32 cmd2 = 0;
    uint32 value = 0;
    uint32 value1 = 0;
    uint32 value2 = 0;
    ds_t fib_engine_lookup_ctl;
    ds_t fib_engine_lookup_result_ctl;
    ds_t ipe_lookup_route_ctl;
    ipv6_addr_t ipv6_addr;
    ipv6_addr_t ipv6_addr_mask;

    sal_memset(&fib_engine_lookup_ctl, 0, sizeof(fib_engine_lookup_ctl));
    sal_memset(&fib_engine_lookup_result_ctl, 0, sizeof(fib_engine_lookup_result_ctl));
    sal_memset(&ipe_lookup_route_ctl, 0, sizeof(ipe_lookup_route_ctl));

    /*L3IF*/
    if (!DRV_IS_DUET2(lchip))
    {
        value = 0;
        cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_vMacMismatchIpv6Discard_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_vMacMismatchIpv4Discard_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_vMacMismatchCheckIpv6En_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_vMacMismatchCheckIpv4En_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_vMacMismatchIpv4ExceptionEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_vMacMismatchIpv6ExceptionEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }
    /*IPUC*/
    cmd = DRV_IOR(FibEngineLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fib_engine_lookup_ctl));
    cmd = DRV_IOW(FibEngineLookupCtl_t, DRV_ENTRY_FLAG);
    SetFibEngineLookupCtl(V, hostUrpfEn_f, fib_engine_lookup_ctl, 1);
    SetFibEngineLookupCtl(V, lpmPipelineEn_f, fib_engine_lookup_ctl, 1);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fib_engine_lookup_ctl));

    cmd = DRV_IOW(IpeRouteCtl_t, IpeRouteCtl_rpfCheckAgainstPort_f);
    value = 0;
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOR(FibEngineLookupResultCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fib_engine_lookup_result_ctl));
    cmd = DRV_IOW(FibEngineLookupResultCtl_t, DRV_ENTRY_FLAG);
    SetFibEngineLookupResultCtl(V, gIpv4UcastLookupResultCtl_defaultEntryBase_f, fib_engine_lookup_result_ctl, 1);
    SetFibEngineLookupResultCtl(V, gIpv4UcastLookupResultCtl_defaultEntryEn_f, fib_engine_lookup_result_ctl, 1);
    SetFibEngineLookupResultCtl(V, gIpv4UcastLookupResultCtl_defaultEntryType_f, fib_engine_lookup_result_ctl, 1);
    SetFibEngineLookupResultCtl(V, gIpv4RpfLookupResultCtl_defaultEntryBase_f, fib_engine_lookup_result_ctl, 1);
    SetFibEngineLookupResultCtl(V, gIpv4RpfLookupResultCtl_defaultEntryEn_f, fib_engine_lookup_result_ctl, 1);
    SetFibEngineLookupResultCtl(V, gIpv4RpfLookupResultCtl_defaultEntryType_f, fib_engine_lookup_result_ctl, 1);
    SetFibEngineLookupResultCtl(V, gIpv6UcastLookupResultCtl_defaultEntryBase_f, fib_engine_lookup_result_ctl, 2);
    SetFibEngineLookupResultCtl(V, gIpv6UcastLookupResultCtl_defaultEntryEn_f, fib_engine_lookup_result_ctl, 1);
    SetFibEngineLookupResultCtl(V, gIpv6UcastLookupResultCtl_defaultEntryType_f, fib_engine_lookup_result_ctl, 1);
    SetFibEngineLookupResultCtl(V, gIpv6RpfLookupResultCtl_defaultEntryBase_f, fib_engine_lookup_result_ctl, 2);
    SetFibEngineLookupResultCtl(V, gIpv6RpfLookupResultCtl_defaultEntryEn_f, fib_engine_lookup_result_ctl, 1);
    SetFibEngineLookupResultCtl(V, gIpv6RpfLookupResultCtl_defaultEntryType_f, fib_engine_lookup_result_ctl, 1);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fib_engine_lookup_result_ctl));

    cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_maxIpv4IcmpLengthEn_f);
    value = 0;
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_maxIpv6IcmpLengthEn_f);
    value = 0;
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_maxIcmpLengthEn_f);
    value = 0;
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOR(IpeLookupRouteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_lookup_route_ctl));
    cmd = DRV_IOW(IpeLookupRouteCtl_t, DRV_ENTRY_FLAG);
    ipv6_addr[0] = 0;
    ipv6_addr[1] = 0;
    ipv6_addr[2] = 0;
    ipv6_addr[3] = 0x3ffe0000;
    SetIpeLookupRouteCtl(A, martianAddr_f, ipe_lookup_route_ctl, ipv6_addr);
    ipv6_addr_mask[0] = 0xffffffff;
    ipv6_addr_mask[1] = 0xffffffff;
    ipv6_addr_mask[2] = 0xffffffff;
    ipv6_addr_mask[3] = 0xffffffff;
    SetIpeLookupRouteCtl(A, martianAddrMask_f, ipe_lookup_route_ctl, ipv6_addr_mask);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_lookup_route_ctl));

    cmd = DRV_IOW(IpeRouteCtl_t, IpeRouteCtl_cloudSecUseShareBit_f);
    value = 1;
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    /*IPMC*/
    cmd1 = DRV_IOW(FibEngineLookupResultCtl_t, FibEngineLookupResultCtl_gIpv4McastLookupResultCtl_defaultEntryBase_f);
    cmd2 = DRV_IOW(FibEngineLookupResultCtl_t, FibEngineLookupResultCtl_gIpv4McastLookupResultCtl_defaultEntryEn_f);
    value1 = 3;
    value2 = 1;
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd1, &value1));
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd2, &value2));

    cmd1 = DRV_IOW(FibEngineLookupResultCtl_t, FibEngineLookupResultCtl_gIpv6McastLookupResultCtl_defaultEntryBase_f);
    cmd2 = DRV_IOW(FibEngineLookupResultCtl_t, FibEngineLookupResultCtl_gIpv6McastLookupResultCtl_defaultEntryEn_f);
    value1 = 0x103;
    value2 = 1;
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd1, &value1));
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd2, &value2));

    cmd1 = DRV_IOW(FibEngineLookupResultCtl_t, FibEngineLookupResultCtl_gIpv4McastLookupResultCtl_defaultEntryType_f);
    cmd2 = DRV_IOW(FibEngineLookupResultCtl_t, FibEngineLookupResultCtl_gIpv6McastLookupResultCtl_defaultEntryType_f);
    value1 = 0;
    value2 = 0;
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd1, &value1));
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd2, &value2));

    cmd = DRV_IOW(IpeRouteCtl_t, IpeRouteCtl_bidiPimGroupType_f);\
    value = 0;
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_register_init_nexthop(uint8 lchip)
{
    int32           cmd = 0;
    uint32          field_value = 0;
    uint32          value = 0;
    uint32 flow_num = 0;
    uint32 flash_crowd_max = 0;
    uint32          chan_id = 0;
    uint32          tbl_id = 0;
    ds_t  ds;

    cmd = DRV_IOR(MetFifoCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetMetFifoCtl(V, groupIdShiftBit_f, ds, 0);
    SetMetFifoCtl(V, portBitmapNextHopPtr_f, ds, 0xFFFC);
    cmd = DRV_IOW(MetFifoCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    sal_memset(ds, 0, sizeof(ds));
    SetDlbEngineCtl(V, reblanceJitterEnable_f, ds, 1);
    SetDlbEngineCtl(V, reblanceJitterThreshold_f, ds, 256);
    SetDlbEngineCtl(V, flashCrowdMitigationEn_f, ds, 0);
    SetDlbEngineCtl(V, reorderPktIntervalMode_f, ds, 1);    /* per 256 packets do reblance */
    SetDlbEngineCtl(V, rebalanceMode_f, ds, 2);
    SetDlbEngineCtl(V, abruptInsertion_f, ds, 1);           /* must be 1 for spec bug */
    SetDlbEngineCtl(V, chanByteCountShift_f, ds, 0);
    SetDlbEngineCtl(V, rebalanceCongestCheck_f, ds, 1);
    SetDlbEngineCtl(V, rebalanceImpactCheck_f, ds, 1);
    SetDlbEngineCtl(V, linkDownSearchPathMode_f, ds, 1);
    SetDlbEngineCtl(V, dlbHashConflictFollowSelfHealing_f, ds, 1);
    if (DRV_FROM_TMM(lchip))
    {
        cmd = DRV_IOW(EcmpDlbEngineCtl_t, DRV_ENTRY_FLAG);
    }
    else
    {
        cmd = DRV_IOW(DlbEngineCtl_t, DRV_ENTRY_FLAG);
    }
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    cmd = DRV_IOR(IpeEcmpCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetIpeEcmpCtl(V, hierarchicalEcmpEn_f, ds, 0);
    SetIpeEcmpCtl(V, dlbIpgEn_f, ds, 1); /* enable dlb ipg */
    SetIpeEcmpCtl(V, memberMoveCheckEn_f, ds, 1);/*member move check*/
    SetIpeEcmpCtl(V, l4ProtocolRrEn_f, ds, 0xFFFF);/* enable ecmp rr for all protocol */
    SetIpeEcmpCtl(V, dlbEnableMode_f, ds, 2);/* All flow do ecmp dlb */
    cmd = DRV_IOW(IpeEcmpCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    if (DRV_FROM_TMM(lchip))
    {
        flow_num = DRV_TABLE_MAX_INDEX(lchip, DsEcmpDlbFlowStateLeft_t)*2 - 1;
        flash_crowd_max = DRV_TABLE_MAX_INDEX(lchip, EcmpDlbChanFlashCrowedS0_t);
        cmd = DRV_IOW(EcmpDlbEngineTimerCtl_t, DRV_ENTRY_FLAG);
    }
    else
    {
        flow_num = DRV_TABLE_MAX_INDEX(lchip, DsDlbFlowStateLeft_t)*2 - 1;
        flash_crowd_max = DRV_TABLE_MAX_INDEX(lchip, DlbChanFlashCrowed_t);
        cmd = DRV_IOW(DlbEngineTimerCtl_t, DRV_ENTRY_FLAG);
    }
    /* Timer1:ecmp dlb flow bandwidth update timer. This flow scan timer must equal to channel bandwidth scan timer,
    it is 100 usec now.  channel bandwidth scan timer refer to _sys_usw_qmgr_dlb_init */
    sal_memset(ds, 0, sizeof(ds));
    SetDlbEngineTimerCtl(V, flowEntryMinPtr_f, ds, 0);
    SetDlbEngineTimerCtl(V, flowEntryMaxPtr_f, ds, flow_num);
    SetDlbEngineTimerCtl(V, chanMaxPtr_f, ds, 127);
    SetDlbEngineTimerCtl(V, flowBandwidthInterval_f, ds, 25);
    SetDlbEngineTimerCtl(V, flowEntryBandwidthMaxPtr_f, ds, flow_num);
    SetDlbEngineTimerCtl(V, flowBandwidthUpdate_f, ds, 1);
    SetDlbEngineTimerCtl(V, cfgRefDivBwRstPulse_f, ds, 25);     /* The pulse timer is 4us. Tsunit is 100usec */
    SetDlbEngineTimerCtl(V, cfgResetDivBwRstPulse_f, ds, 0);
    /* Timer2:ecmp flow inactive timer. TsUnit = 30 ms */
    SetDlbEngineTimerCtl(V, flowStateInactiveInterval_f, ds, 20);
    SetDlbEngineTimerCtl(V, flowStateInactiveMaxPtr_f, ds, flow_num);
    SetDlbEngineTimerCtl(V, flowStateInactiveUpdateEn_f, ds, 1);
    SetDlbEngineTimerCtl(V, flowInactiveTsThreshold_f, ds, 2);          /* For metro, flow inactive time is 60 ms */
    SetDlbEngineTimerCtl(V, cfgRefDivInactiveRstPulse_f, ds, 7500);     /* TsUnit = 30 ms */
    SetDlbEngineTimerCtl(V, cfgResetDivInactiveRstPulse_f, ds, 0);
    /* Timer3:ecmp flow aging timer. TsUnit = 1 s*/
    SetDlbEngineTimerCtl(V, flowEntryAgingInterval_f, ds, 100);
    SetDlbEngineTimerCtl(V, flowEntryAgingMaxPtr_f, ds, flow_num);
    SetDlbEngineTimerCtl(V, flowEntryAgingUpdEn_f, ds, 1);
    SetDlbEngineTimerCtl(V, cfgRefDivAgingRstPulse_f, ds, 250000);      /* TsUnit = 1 s */
    SetDlbEngineTimerCtl(V, cfgResetDivAgingRstPulse_f, ds, 0);

    /* Timer4:flash crowd, Tf = 100us, it need farther less than DRE update period, but cannot get it for the freq */
    SetDlbEngineTimerCtl(V, flashCrowdInterval_f, ds, 25);           /* must big than 73 for 64byte flow */
    SetDlbEngineTimerCtl(V, flashCrowdMaxPtr_f, ds, flash_crowd_max);
    SetDlbEngineTimerCtl(V, flashCrowdUpdEn_f, ds, 1);
    SetDlbEngineTimerCtl(V, cfgRefDivFlashCrowedRstPulse_f, ds, 25);     /* TsUnit = 100 us */
    SetDlbEngineTimerCtl(V, cfgResetDivFlashCrowedRstPulse_f, ds, 0);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));


    if (DRV_FROM_AT(lchip))
    {
        RefDivSlice0PPPulse_m ref_div_pp_pulse;
        value = (625 * 25) << 8;
        cmd = DRV_IOR(RefDivSlice0PPPulse_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ref_div_pp_pulse));
        SetRefDivSlice0PPPulse(V, cfgSlice0RefDivDlbPulse_f, &ref_div_pp_pulse, value);
        SetRefDivSlice0PPPulse(V, cfgSlice0ResetDivDlbPulse_f, &ref_div_pp_pulse, 0);
        SetRefDivSlice0PPPulse(V, cfgSlice0RefDivEpeHdrEditAqmScanPulse_f, &ref_div_pp_pulse, value);
        SetRefDivSlice0PPPulse(V, cfgSlice0ResetDivEpeHdrEditAqmScanPulse_f, &ref_div_pp_pulse, 0);
        cmd = DRV_IOW(RefDivSlice0PPPulse_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ref_div_pp_pulse));
        cmd = DRV_IOW(RefDivSlice1PPPulse_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ref_div_pp_pulse));
        cmd = DRV_IOW(RefDivSlice2PPPulse_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ref_div_pp_pulse));
        cmd = DRV_IOW(RefDivSlice3PPPulse_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ref_div_pp_pulse));
    }
    else
    {
        /* Config pulse timer to 4us, low 8 bit is decimal fraction 156.25MHz/625=250kHz(4us)*/
        value = 625 << 8;
        cmd = DRV_IOW(RefDivDlbPulse_t, RefDivDlbPulse_cfgRefDivDlbPulse_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        value = 0;
        cmd = DRV_IOW(RefDivDlbPulse_t, RefDivDlbPulse_cfgResetDivDlbPulse_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }

    value = 1;
    tbl_id = DRV_FROM_AT(lchip) ? EcmpDlbLinkState_t : (DRV_IS_TMM(lchip) ? EcmpDlbChanStateCtl_t : DlbChanStateCtl_t);
    cmd = DRV_IOW(tbl_id, DlbChanStateCtl_linkState_f);
    for(chan_id=0; chan_id < MCHIP_CAP(SYS_CAP_CHANNEL_NUM); chan_id++)
    {
        if (!SYS_IS_NETWORK_CHANNEL(chan_id))
        {
            continue;
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, chan_id, cmd, &value));
    }

    /*For CoSim*/
    sal_memset(ds, 0, sizeof(ds));
    cmd = DRV_IOW(DsL23Edit3W_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    /*Epe Head Adjust Ctl init*/
    cmd = DRV_IOR(EpeHdrAdjustCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetEpeHdrAdjustCtl(V, natStackingEn_f, ds, 1);
    SetEpeHdrAdjustCtl(V, dsNextHopInternalBase_f, ds, 0xFFF);
    cmd = DRV_IOW(EpeHdrAdjustCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    cmd = DRV_IOR(EpeNextHopCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetEpeNextHopCtl(V, capwapBridgeOperation_f, ds, 1);
    SetEpeNextHopCtl(V, innerEditPtrAdjEn_f, ds, 1);
    SetEpeNextHopCtl(V, egressVlanStatsMode_f, ds, 1);
    SetEpeNextHopCtl(V, isLeafShareMatrix_0_shareInfo_f, &ds, 0x0); // AT
    SetEpeNextHopCtl(V, isLeafShareMatrix_1_shareInfo_f, &ds, 0x1); // AT
    value = 0;
    CTC_BIT_SET(value, SYS_PARSER_EXT_TYPE_SRV6);
    SetEpeNextHopCtl(V, extractDataHighEn_f, ds, value);
    cmd = DRV_IOW(EpeNextHopCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    if (DRV_IS_TMM(lchip))
    {
        cmd = DRV_IOR(EpeHdrProcReserved_t, EpeHdrProcReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        value |= (1<<0);
        cmd = DRV_IOW(EpeHdrProcReserved_t, EpeHdrProcReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }
    if (DRV_IS_TSINGMA(lchip) && (SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A))
    {
        cmd = DRV_IOR(IpeFwdReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        field_value = GetIpeFwdReserved(V, reserved_f, ds);
        field_value &= 0xffffe3f;
        field_value |= (4 << 6);
        SetIpeFwdReserved(V, reserved_f, ds, field_value);
        cmd = DRV_IOW(IpeFwdReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    }

    cmd = DRV_IOR(EpePktProcProtocolMapCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetEpePktProcProtocolMapCtl(V, g_0_eType_f, &ds, 0x6558);
    SetEpePktProcProtocolMapCtl(V, g_0_proto0_f, &ds, 3);
    SetEpePktProcProtocolMapCtl(V, g_1_eType_f, &ds, 0x0800);
    SetEpePktProcProtocolMapCtl(V, g_1_proto0_f, &ds, 1);
    SetEpePktProcProtocolMapCtl(V, g_2_eType_f, &ds, 0x8847);
    SetEpePktProcProtocolMapCtl(V, g_3_eType_f, &ds, 0x86dd);
    SetEpePktProcProtocolMapCtl(V, g_3_proto0_f, &ds, 2);
    SetEpePktProcProtocolMapCtl(V, g_4_eType_f, &ds, 0x8848);
    cmd = DRV_IOW(EpePktProcProtocolMapCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(EpeNextHopCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    tbl_id = DRV_IS_AT(lchip) ? DsL3EditRwIp41X0_t : DsL3EditRwIp41X_t;
    value = (DRV_TABLE_MAX_INDEX(lchip, tbl_id) > SYS_SNAT_EDIT_PTR_BASE)? /*snatEditPtr(13,0)*/
                  (DRV_TABLE_MAX_INDEX(lchip, tbl_id) - SYS_SNAT_EDIT_PTR_BASE):0;
    SetEpeNextHopCtl(V, snatEditPtrType_f, &ds, 1);
    SetEpeNextHopCtl(V, snatEditPtrBase_f, &ds, value);
    cmd = DRV_IOW(EpeNextHopCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    cmd = DRV_IOR(EpeNextHopInternal_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 6, cmd, ds));
    SetEpeNextHopInternal(V, cvlanTagged_f, ds, 1);
    SetEpeNextHopInternal(V, innerEditPtr_f, ds, 8);
    SetEpeNextHopInternal(V, logicDestPort_f, ds, 0x800);
    SetEpeNextHopInternal(V, payloadOperation_f, ds, 2);
    SetEpeNextHopInternal(V, shareType_f, ds, 1);
    SetEpeNextHopInternal(V, svlanTagged_f, ds, 1);
    SetEpeNextHopInternal(V, u1_g2_deriveStagCos_f, ds, 1);
    cmd = DRV_IOW(EpeNextHopInternal_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 6, cmd, ds));

    cmd = DRV_IOR(PreMetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetPreMetCtl(V, preMetEn_f,   &ds, 0);
    cmd = DRV_IOW(PreMetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    for (value = 0; value < SYS_PP_NUM(lchip); value++)
    {
        cmd = DRV_IOR(PreMetVecCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip + value, 0, DRV_CMD_PP_EN(cmd), &ds));
#ifdef EMULATION_ENV
        SetPreMetVecCtl(V, repVec_f, &ds, 1 << (value & (PP_NUM_PER_CORE - 1)));
        SetPreMetVecCtl(V, repVecExcp_f, &ds, 1 << (value & (PP_NUM_PER_CORE - 1)));
#else
        SetPreMetVecCtl(V, repVec_f, &ds, 0x1);/*always to pp0*/
        SetPreMetVecCtl(V, repVecExcp_f, &ds, 0x1);/*always to pp0*/
#endif
        cmd = DRV_IOW(PreMetVecCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip + value, 0, DRV_CMD_PP_EN(cmd), &ds));
    }
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_register_init_qos_resrc(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint16 index  = 0;
    uint16 index1  = 0;
    uint32 entry_num = 0;
    uint8 mcast = 0;
    uint8 dp = 0;
    uint8 sc = 0;
    uint8 priority = 0;
    uint8 color = 0;
    uint8 cutthrough_enable = 0;
    uint8 step = 0;
    uint8 type_num = 0;
    IrmMiscCtl_m irm_misc_ctl;
    ErmMiscCtl_m erm_misc_ctl;
    DsErmAqmQueueThrdProfile_m erm_aqm_thrd;
    DsErmQueueLimitedThrdProfile_m ds_que_thrd_profile;
    DsErmPortLimitedThrdProfile_m erm_port_limit_prof;
    DsIrmPortLimitedThrdProfile_m ds_port_thrd_profile;
    DsIrmPortTcLimitedThrdProfile_m ds_porttc_thrd_profile;
    DsIrmPortFlowControlThrdProfile_m fc_profile;
    DsErmPortFcCfg_m ds_egr_port_tc_fc_profile;
    DsIrmMiscThrd_m irm_misc_thrd;
    DsIrmScThrd_m irm_sc_thrd;
    DsIrmPrioScTcMap_m irm_prio_sc_tc_map;
    DsIrmColorDpMap_m irm_color_dp_map;
    DsErmScThrd_m erm_sc_thrd;
    DsErmPrioScTcMap_m erm_prio_sc_tc_map;
    DsErmColorDpMap_m erm_color_dp_map;
    DsErmMiscThrd_m erm_misc_thrd;
    /*random seed*/
    uint8  drop_sed[256] =
    {
        74, 68, 39, 50, 3 , 78, 34, 38, 96, 36,
        44, 86, 15, 29, 13, 78, 18, 19, 22, 78,
        76, 7 , 44, 49, 74, 54, 56, 62, 16, 74,
        73, 8 , 30, 83, 13, 21, 91, 38, 62, 3 ,
        10, 25, 7 , 2 , 58, 11, 81, 40, 54, 73,
        96, 20, 32, 84, 1 , 24, 67, 43, 69, 58,
        60, 57, 2 , 44, 73, 94, 36, 88, 13, 20,
        24, 55, 6 , 65, 40, 97, 57, 54, 77, 41,
        62, 53, 78, 79, 78, 2 , 77, 93, 93, 26,
        51, 60, 53, 73, 83, 65, 72, 2 , 75, 43,
        63, 98, 2 , 93, 19, 88, 50, 64, 81, 86,
        22, 23, 70, 84, 88, 28, 87, 26, 39, 39,
        15, 44, 19, 12, 3 , 50, 76, 72, 74, 14,
        76, 17, 63, 36, 84, 77, 14, 61, 96, 92,
        99, 67, 68, 40, 63, 42, 63, 46, 29, 64,
        35, 32, 31, 41, 55, 81, 96, 49, 79, 91,
        48, 60, 88, 82, 11, 77, 15, 38, 72, 35,
        38, 43, 49, 31, 37, 12, 43, 2 , 57, 4 ,
        54, 81, 57, 65, 74, 2 , 92, 96, 89, 15,
        18, 4 , 17, 59, 15, 36, 27, 88, 34, 30,
        24, 96, 99, 49, 8 , 83, 84, 36, 63, 25,
        60, 23, 10, 90, 16, 38, 2 , 25, 35, 39,
        20, 62, 49, 9 , 80, 97, 81, 95, 16, 50,
        60, 22, 80, 12, 73, 30, 48, 81, 79, 3 ,
        33, 1 , 96, 17, 44, 36, 27, 46, 46, 76,
        46, 68, 21, 65, 45, 54
    };

    sal_memset(&irm_misc_ctl, 0, sizeof(IrmMiscCtl_m));
    sal_memset(&erm_misc_ctl, 0, sizeof(ErmMiscCtl_m));
    sal_memset(&erm_aqm_thrd, 0, sizeof(DsErmAqmQueueThrdProfile_m));
    sal_memset(&ds_que_thrd_profile, 0, sizeof(DsErmQueueLimitedThrdProfile_m));
    sal_memset(&erm_port_limit_prof, 0, sizeof(DsErmPortLimitedThrdProfile_m));
    sal_memset(&ds_porttc_thrd_profile, 0, sizeof(DsIrmPortTcLimitedThrdProfile_m));
    sal_memset(&ds_port_thrd_profile, 0, sizeof(DsIrmPortLimitedThrdProfile_m));
    sal_memset(&fc_profile, 0, sizeof(DsIrmPortFlowControlThrdProfile_m));
    sal_memset(&irm_misc_thrd, 0, sizeof(DsIrmMiscThrd_m));
    sal_memset(&irm_sc_thrd, 0, sizeof(DsIrmScThrd_m));
    sal_memset(&irm_prio_sc_tc_map, 0, sizeof(DsIrmPrioScTcMap_m));
    sal_memset(&irm_color_dp_map, 0, sizeof(DsIrmColorDpMap_m));
    sal_memset(&erm_sc_thrd, 0, sizeof(DsErmScThrd_m));
    sal_memset(&erm_prio_sc_tc_map, 0, sizeof(DsErmPrioScTcMap_m));
    sal_memset(&erm_color_dp_map, 0, sizeof(DsErmColorDpMap_m));
    sal_memset(&erm_misc_thrd, 0, sizeof(DsErmMiscThrd_m));
    sal_memset(&ds_egr_port_tc_fc_profile, 0, sizeof(DsErmPortFcCfg_m));

    cutthrough_enable = sys_usw_chip_get_cut_through_en(lchip);
    /* 1. config ingress resource management*/
    /*TMM*/
    SetIrmMiscCtl(V, c2cPacketPortTcEn_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, c2cPacketScEn_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, c2cPacketSc_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, c2cPacketTcEn_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, c2cPacketTc_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, continuousPortUseScRemain_f , &irm_misc_ctl, 1);
    SetIrmMiscCtl(V, criticalPacketPortTcEn_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, criticalPacketScEn_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, criticalPacketSc_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, criticalPacketTcEn_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, criticalPacketTc_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, flowControlScEn_f , &irm_misc_ctl, 1);
    SetIrmMiscCtl(V, flowControlUsePortCnt_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, glbPortLimitedDis_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, glbPortScGuaranteedDis_f , &irm_misc_ctl, 1);
    SetIrmMiscCtl(V, glbPortScLimitedDis_f , &irm_misc_ctl, 1);
    SetIrmMiscCtl(V, glbPortTcLimitedDis_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, totalExcludeGuarantee_f , &irm_misc_ctl, 1);
    SetIrmMiscCtl(V, c2cPacketDpEn_f , &irm_misc_ctl, 1);
    SetIrmMiscCtl(V, c2cPacketDp_f , &irm_misc_ctl, 3);
    SetIrmMiscCtl(V, continuousPortTcUseScRemain_f , &irm_misc_ctl, 1);
    SetIrmMiscCtl(V, criticalPacketDpEn_f , &irm_misc_ctl, 1);
    SetIrmMiscCtl(V, criticalPacketDp_f , &irm_misc_ctl, 3);
    SetIrmMiscCtl(V, localPhyPortResrcBase_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, localPhyPortResrcEn_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, localPhyPortResrcPriEn_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, noCareC2cPacket_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, noCareCriticalPacket_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, resourceCheckEn_f , &irm_misc_ctl, 1);
    SetIrmMiscCtl(V, resourceCheckMode_f , &irm_misc_ctl, 1); /*TM*/
    SetIrmMiscCtl(V, resrcUseCntMin_f , &irm_misc_ctl, 2);
    SetIrmMiscCtl(V, scExcludeGuarantee_f , &irm_misc_ctl, 1);
    SetIrmMiscCtl(V, glbPortTcGuaranteedDis_f , &irm_misc_ctl, 0);
    SetIrmMiscCtl(V, guaranteedMode_f, &irm_misc_ctl, 7);/*bit0:porttc 1:portsc 2:port guarantee*/
    SetIrmMiscCtl(V, thrdPassMode_f, &irm_misc_ctl, 7);
    cmd = DRV_IOW(IrmMiscCtl_t, DRV_ENTRY_FLAG);
    SYS_SET_TBL_ALL_DP(lchip, cmd, irm_misc_ctl);

    SetDsIrmMiscThrd(V, c2cThrd_f, &irm_misc_thrd, 1280);
    SetDsIrmMiscThrd(V, criticalThrd_f, &irm_misc_thrd, 1280);
    SetDsIrmMiscThrd(V, totalThrd_f, &irm_misc_thrd, MCHIP_CAP(SYS_CAP_QOS_DROP_TOTAL_POOL_SIZE));
    cmd = DRV_IOW(DsIrmMiscThrd_t, DRV_ENTRY_FLAG);
    SYS_SET_TBL_ALL_DP(lchip, cmd, irm_misc_thrd);

    SetDsIrmScThrd(V, scEn_f, &irm_sc_thrd, 1);
    SetDsIrmScThrd(V, scThrd_f, &irm_sc_thrd, 72192);
    cmd = DRV_IOW(DsIrmScThrd_t, DRV_ENTRY_FLAG);
    for (dp = 0; dp < MCHIP_CAP(SYS_CAP_DP_MAX_NUM); dp++)
    {
        index = dp << 2 | CTC_QOS_IGS_RESRC_DEFAULT_POOL;
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &irm_sc_thrd));
    }

    /* 5. mapping profiles, only use profile 0: all priority mapped to tc priority/2 and sc 0 */
    for (dp = 0; dp < MCHIP_CAP(SYS_CAP_DP_MAX_NUM); dp++)
    {
        for (mcast = 0; mcast < 2; mcast++)
        {
            for (priority = 0; priority < 16; priority++)
            {
                index = dp << 5 | mcast << 4 | priority;
                sc = CTC_QOS_EGS_RESRC_DEFAULT_POOL;
                SetDsIrmPrioScTcMap(V, g2_0_mappedTc_f, &irm_prio_sc_tc_map, priority / 2);
                SetDsIrmPrioScTcMap(V, g2_0_portTcEn_f, &irm_prio_sc_tc_map, mcast ? 0 : 1);
                SetDsIrmPrioScTcMap(V, g1_0_mappedSc_f , &irm_prio_sc_tc_map, sc);
                cmd = DRV_IOW(DsIrmPrioScTcMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &irm_prio_sc_tc_map));
            }
        }
    }
    for (dp = 0; dp < MCHIP_CAP(SYS_CAP_DP_MAX_NUM); dp++)
    {
        for (mcast = 0; mcast < 2; mcast++)
        {
            for (color = 0; color < 4; color++)
            {
                index = dp << 3 | mcast << 2 | color;
                field_val = (color + 3) % 4;
                SetDsIrmColorDpMap(V, g_0_dropPrecedence_f, &irm_color_dp_map, field_val);
                cmd = DRV_IOW(DsIrmColorDpMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &irm_color_dp_map));
            }
        }
    }

    for (index = 0; index < MCHIP_CAP(SYS_CAP_CHANNEL_NUM); index++)
    {
        field_val = 0;
        cmd = DRV_IOW(DsIrmChannel_t, DsIrmChannel_irmProfId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &field_val));
    }

    /* 2. config egress resource management*/
    /*TMM*/
    SetErmMiscCtl(V, aqmSeedUpdateEn_f , &erm_misc_ctl, 0xF0);
    SetErmMiscCtl(V, c2cPacketScEn_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, c2cPacketSc_f, &erm_misc_ctl, CTC_QOS_EGS_RESRC_CONTROL_POOL);
    SetErmMiscCtl(V, c2cPacketTcEn_f, &erm_misc_ctl, 0);
    SetErmMiscCtl(V, c2cPacketTc_f, &erm_misc_ctl, 0);
    SetErmMiscCtl(V, continuousPortUseScRemain_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, continuousQueueUseScRemain_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, criticalPacketScEn_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, criticalPacketSc_f, &erm_misc_ctl, CTC_QOS_EGS_RESRC_CONTROL_POOL);
    SetErmMiscCtl(V, criticalPacketTcEn_f, &erm_misc_ctl, 0);
    SetErmMiscCtl(V, criticalPacketTc_f, &erm_misc_ctl, 0);
    SetErmMiscCtl(V, glbPortLimitedDis_f, &erm_misc_ctl, 0);
    SetErmMiscCtl(V, glbPortScGuaranteedDis_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, glbPortScLimitedDis_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, totalExcludeGuarantee_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, aqmPortUseAvgEn_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, basedOnCellCnt_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, c2cPacketDpEn_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, c2cPacketDp_f, &erm_misc_ctl, 3);
    SetErmMiscCtl(V, continuousPortTcUseScRemain_f, &erm_misc_ctl, ((DRV_IS_DUET2(lchip)&&cutthrough_enable)?0:1));
    SetErmMiscCtl(V, criticalPacketDpEn_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, criticalPacketDp_f, &erm_misc_ctl, 3);
    SetErmMiscCtl(V, ignoreAvqMaxThrdCheck_f, &erm_misc_ctl, 0);
    SetErmMiscCtl(V, microBurstInformEn_f, &erm_misc_ctl, 0);
    SetErmMiscCtl(V, noCareC2cPacket_f, &erm_misc_ctl, 1);/* c2c packet use sc pool*/
    SetErmMiscCtl(V, noCareCriticalPacket_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, notEctPacketDpEn_f, &erm_misc_ctl, 0);
    SetErmMiscCtl(V, notEctPacketDp_f, &erm_misc_ctl, 3);
    SetErmMiscCtl(V, resourceCheckEn_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, resourceCheckMode_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, resrcUseCntMin_f, &erm_misc_ctl, 2);
    SetErmMiscCtl(V, glbQueueGuaranteedDis_f, &erm_misc_ctl, 0); /*default use port min, not use queue min*/
    SetErmMiscCtl(V, scExcludeGuarantee_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, aqmExcludeGuarantee_f, &erm_misc_ctl, 1);
    SetErmMiscCtl(V, glbAqmQueueDis_f, &erm_misc_ctl, ((DRV_IS_DUET2(lchip)&&cutthrough_enable)?1:0));
    SetErmMiscCtl(V, guaranteedMode_f, &erm_misc_ctl, 7);/*bit0:porttc 1:portsc 2:port guarantee*/
    SetErmMiscCtl(V, thrdPassMode_f, &erm_misc_ctl, 7);
    SetErmMiscCtl(V, baseQueueMax_f, &erm_misc_ctl, MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_EXCP) - 1);
    SetErmMiscCtl(V, baseQueueMin_f, &erm_misc_ctl, 0);
    cmd = DRV_IOW(ErmMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_misc_ctl));

    SetDsErmMiscThrd(V, c2cThrd_f, &erm_misc_thrd, 1024);
    SetDsErmMiscThrd(V, criticalThrd_f, &erm_misc_thrd, 1024);
    SetDsErmMiscThrd(V, spanThrd_f, &erm_misc_thrd, 0x400);
    SetDsErmMiscThrd(V, totalThrd_f, &erm_misc_thrd, MCHIP_CAP(SYS_CAP_QOS_DROP_TOTAL_POOL_SIZE));
    cmd = DRV_IOW(DsErmMiscThrd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_misc_thrd));

    SetDsErmScThrd(V, g_0_scThrd_f, &erm_sc_thrd, MCHIP_CAP(SYS_CAP_QOS_DROP_EGS_DEFAULT_POOL_SIZE) / 8);
    SetDsErmScThrd(V, g_1_scThrd_f, &erm_sc_thrd, 0);
    SetDsErmScThrd(V, g_2_scThrd_f, &erm_sc_thrd, 0);
    SetDsErmScThrd(V, g_3_scThrd_f, &erm_sc_thrd, 2048 / 8);
    SetDsErmScThrd(V, g_0_scEn_f, &erm_sc_thrd, 1);
    SetDsErmScThrd(V, g_1_scEn_f, &erm_sc_thrd, 0);
    SetDsErmScThrd(V, g_2_scEn_f, &erm_sc_thrd, 0);
    SetDsErmScThrd(V, g_3_scEn_f, &erm_sc_thrd, 1);
    SetDsErmScThrd(V, g_0_scCngThrd_f, &erm_sc_thrd, 0x7ff);
    SetDsErmScThrd(V, g_1_scCngThrd_f, &erm_sc_thrd, 0x7ff);
    SetDsErmScThrd(V, g_2_scCngThrd_f, &erm_sc_thrd, 0x7ff);
    SetDsErmScThrd(V, g_3_scCngThrd_f, &erm_sc_thrd, 0x7ff);
    SetDsErmScThrd(V, g_0_scCngEn_f, &erm_sc_thrd, 0);
    SetDsErmScThrd(V, g_1_scCngEn_f, &erm_sc_thrd, 0);
    SetDsErmScThrd(V, g_2_scCngEn_f, &erm_sc_thrd, 0);
    SetDsErmScThrd(V, g_3_scCngEn_f, &erm_sc_thrd, 0);
    cmd = DRV_IOW(DsErmScThrd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_sc_thrd));

    type_num = DRV_FROM_TMM(lchip) ? 8 : 2;
    for (mcast = 0; mcast < type_num; mcast++)
    {
        for (priority = 0; priority < 16; priority++)
        {
            index = mcast << 4 | priority;
            sc = CTC_QOS_EGS_RESRC_DEFAULT_POOL;
            SetDsErmPrioScTcMap(V, g2_0_mappedTc_f, &erm_prio_sc_tc_map, priority / 2);
            SetDsErmPrioScTcMap(V, g1_0_mappedSc_f , &erm_prio_sc_tc_map, sc);
            SetDsErmPrioScTcMap(V, g2_3_mappedTc_f, &erm_prio_sc_tc_map, priority / 2);
            SetDsErmPrioScTcMap(V, g1_3_mappedSc_f , &erm_prio_sc_tc_map, sc);
            SetDsErmPrioScTcMap(V, g2_4_mappedTc_f, &erm_prio_sc_tc_map, priority / 2);
            SetDsErmPrioScTcMap(V, g1_4_mappedSc_f , &erm_prio_sc_tc_map, sc);
            SetDsErmPrioScTcMap(V, g2_5_mappedTc_f, &erm_prio_sc_tc_map, priority / 2);
            SetDsErmPrioScTcMap(V, g1_5_mappedSc_f , &erm_prio_sc_tc_map, sc);
            SetDsErmPrioScTcMap(V, g2_6_mappedTc_f, &erm_prio_sc_tc_map, priority / 2);
            SetDsErmPrioScTcMap(V, g1_6_mappedSc_f , &erm_prio_sc_tc_map, sc);
            SetDsErmPrioScTcMap(V, g2_7_mappedTc_f, &erm_prio_sc_tc_map, priority / 2);
            SetDsErmPrioScTcMap(V, g1_7_mappedSc_f , &erm_prio_sc_tc_map, sc);
            cmd = DRV_IOW(DsErmPrioScTcMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &erm_prio_sc_tc_map));
        }
    }

    for (mcast = 0; mcast < type_num; mcast++)/*SYS_QUE_MAP_TYPE_MAX_NUM*/
    {
        for (color = 0; color < 4; color++)/*MAX_CTC_QOS_COLOR*/
        {
            index = mcast << 2 | color;
            if(mcast == 0 || mcast == 1 || mcast ==2 || mcast == 6)/*SYS_QUE_MAP_TYPE_UC|| SYS_QUE_MAP_TYPE_MC ||SYS_QUE_MAP_TYPE_SPAN*/
            {
                field_val = (color + 3) % 4;
            }
            else
            {
                field_val = 3;
            }
            SetDsErmColorDpMap(V, g_0_dropPrecedence_f, &erm_color_dp_map, field_val);
            SetDsErmColorDpMap(V, g_1_dropPrecedence_f, &erm_color_dp_map, field_val);
            SetDsErmColorDpMap(V, g_2_dropPrecedence_f, &erm_color_dp_map, field_val);
            SetDsErmColorDpMap(V, g_3_dropPrecedence_f, &erm_color_dp_map, field_val);
            SetDsErmColorDpMap(V, g_4_dropPrecedence_f, &erm_color_dp_map, field_val);
            SetDsErmColorDpMap(V, g_5_dropPrecedence_f, &erm_color_dp_map, field_val);
            SetDsErmColorDpMap(V, g_6_dropPrecedence_f, &erm_color_dp_map, field_val);
            SetDsErmColorDpMap(V, g_7_dropPrecedence_f, &erm_color_dp_map, field_val);
            cmd = DRV_IOW(DsErmColorDpMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &erm_color_dp_map));
        }
    }
    for (index = 0; index < MCHIP_CAP(SYS_CAP_CHANNEL_NUM); index++)
    {
        field_val = index;
        cmd = DRV_IOW(DsErmChannel_t, DsErmChannel_queueBase_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &field_val));
    }

    if(DRV_FROM_TMM(lchip))
    {
        ds_t ds = {0};
        /*queue min*/
        field_val = 0x3FF;
        SetDsErmQueueGuaranteedThrdProfile(V, queueGuaranteedThrd_f, ds, field_val);
        cmd = DRV_IOW(DsErmQueueGuaranteedThrdProfile_t, DRV_ENTRY_FLAG);
        /*base + dma queue*/
        for (index = 0; index < MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_EXCP) + 128; index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, ds));
        }
        for (index = MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_NETWORK_MISC); index < MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM); index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, ds));
        }

        /*irm port min*/
        field_val = 30;
        sys_usw_ftm_query_table_entry_num(lchip, DsIrmPortGuaranteedThrdProfile_t, &entry_num);
        for (index = 0; index < entry_num; index++)
        {
            cmd = DRV_IOW(DsIrmPortGuaranteedThrdProfile_t, DsIrmPortGuaranteedThrdProfile_portGuaranteedThrd_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &field_val));
        }

        /*erm port min*/
        field_val = 30;
        SetDsErmPortGuaranteedThrdProfile(V, portGuaranteedThrd_f, ds, field_val);
        sys_usw_ftm_query_table_entry_num(lchip, DsErmPortGuaranteedThrdProfile_t, &entry_num);
        cmd = DRV_IOW(DsErmPortGuaranteedThrdProfile_t, DRV_ENTRY_FLAG);
        for (index = 0; index < entry_num; index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, ds));
        }

        /*TMM*/
        cmd = DRV_IOW(DsErmMiscThrd_t, DsErmMiscThrd_portCongestionThrd_f);
        field_val = 20;
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));


        /*TMM default disable wred*/
        field_val = DRV_FROM_AT(lchip) ? 0x1FFFF: 0x3FFF;
        SetDsErmAqmQueueThrdProfile(V, g_0_wredAvgMaxLen_f, &erm_aqm_thrd, field_val);
        SetDsErmAqmQueueThrdProfile(V, g_1_wredAvgMaxLen_f, &erm_aqm_thrd, field_val);
        SetDsErmAqmQueueThrdProfile(V, g_2_wredAvgMaxLen_f, &erm_aqm_thrd, field_val);
        SetDsErmAqmQueueThrdProfile(V, g_3_wredAvgMaxLen_f, &erm_aqm_thrd, field_val);
        cmd = DRV_IOW(DsErmAqmQueueThrdProfile_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_aqm_thrd));

        /*TMM wred config random seed*/
        sys_usw_ftm_query_table_entry_num(lchip, DsErmAqmQueueSeed_t, &entry_num);
        cmd = DRV_IOW(DsErmAqmQueueSeed_t, DsErmAqmQueueSeed_seed_f);
        for (index = 0; index < entry_num; index++)
        {
            SetDsErmAqmQueueSeed(V, seed_f, ds, drop_sed[index]);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, ds));
        }

        /*TMM default disable erm ecn mark*/
        field_val = MCHIP_CAP(SYS_CAP_QOS_QUEUE_MAX_DROP_THRD) / 8;
        SetDsErmQueueLimitedThrdProfile(V, g_0_ecnMarkThrd_f , &ds_que_thrd_profile, field_val);
        SetDsErmQueueLimitedThrdProfile(V, g_1_ecnMarkThrd_f , &ds_que_thrd_profile, field_val);
        SetDsErmQueueLimitedThrdProfile(V, g_2_ecnMarkThrd_f , &ds_que_thrd_profile, field_val);
        SetDsErmQueueLimitedThrdProfile(V, g_3_ecnMarkThrd_f , &ds_que_thrd_profile, field_val);
        SetDsErmQueueLimitedThrdProfile(V, g_0_queueLimitedAutoEn_f , &ds_que_thrd_profile, 1);
        SetDsErmQueueLimitedThrdProfile(V, g_1_queueLimitedAutoEn_f , &ds_que_thrd_profile, 1);
        SetDsErmQueueLimitedThrdProfile(V, g_2_queueLimitedAutoEn_f , &ds_que_thrd_profile, 1);
        SetDsErmQueueLimitedThrdProfile(V, g_3_queueLimitedAutoEn_f , &ds_que_thrd_profile, 1);
        cmd = DRV_IOW(DsErmQueueLimitedThrdProfile_t, DRV_ENTRY_FLAG);
        /*base + dma queue*/
        for (index = 0; index < MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_EXCP) + 128; index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds_que_thrd_profile));
        }
        for (index = MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_NETWORK_MISC); index < MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM); index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds_que_thrd_profile));
        }

        /*TMM default disable erm port thrd check*/
        sys_usw_ftm_query_table_entry_num(lchip, DsErmPortLimitedThrdProfile_t, &entry_num);
        field_val = 0x3FFF;
        SetDsErmPortLimitedThrdProfile(V, g_0_portLimitedThrd_f, &erm_port_limit_prof, field_val);
        SetDsErmPortLimitedThrdProfile(V, g_1_portLimitedThrd_f, &erm_port_limit_prof, field_val);
        SetDsErmPortLimitedThrdProfile(V, g_2_portLimitedThrd_f, &erm_port_limit_prof, field_val);
        SetDsErmPortLimitedThrdProfile(V, g_3_portLimitedThrd_f, &erm_port_limit_prof, field_val);
        cmd = DRV_IOW(DsErmPortLimitedThrdProfile_t, DRV_ENTRY_FLAG);
        for (index = 0; index < entry_num; index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &erm_port_limit_prof));
        }

        /*TMM default disable irm portTc limited thrd check*/
        sys_usw_ftm_query_table_entry_num(lchip, DsIrmPortTcLimitedThrdProfile_t, &entry_num);
        field_val = 0x3FFF;
        SetDsIrmPortTcLimitedThrdProfile(V, g_0_portTcLimitedThrd_f , &ds_porttc_thrd_profile, field_val);
        SetDsIrmPortTcLimitedThrdProfile(V, g_1_portTcLimitedThrd_f , &ds_porttc_thrd_profile, field_val);
        SetDsIrmPortTcLimitedThrdProfile(V, g_2_portTcLimitedThrd_f , &ds_porttc_thrd_profile, field_val);
        SetDsIrmPortTcLimitedThrdProfile(V, g_3_portTcLimitedThrd_f , &ds_porttc_thrd_profile, field_val);
        cmd = DRV_IOW(DsIrmPortTcLimitedThrdProfile_t, DRV_ENTRY_FLAG);
        for (index = 0; index < entry_num; index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds_porttc_thrd_profile));
        }

        /*TMM default disable irm port limited thrd check*/
        sys_usw_ftm_query_table_entry_num(lchip, DsIrmPortLimitedThrdProfile_t, &entry_num);
        field_val = 0x3FFF;
        SetDsIrmPortLimitedThrdProfile(V, g_0_portLimitedThrd_f , &ds_port_thrd_profile, field_val);
        SetDsIrmPortLimitedThrdProfile(V, g_1_portLimitedThrd_f , &ds_port_thrd_profile, field_val);
        SetDsIrmPortLimitedThrdProfile(V, g_2_portLimitedThrd_f , &ds_port_thrd_profile, field_val);
        SetDsIrmPortLimitedThrdProfile(V, g_3_portLimitedThrd_f , &ds_port_thrd_profile, field_val);
        cmd = DRV_IOW(DsIrmPortLimitedThrdProfile_t, DRV_ENTRY_FLAG);
        for (index = 0; index < entry_num; index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds_port_thrd_profile));
        }

        /*TMM default pc/pfc thrd */
        sys_usw_ftm_query_table_entry_num(lchip, DsIrmPortFlowControlThrdProfile_t, &entry_num);
        step = DsIrmPortFlowControlThrdProfile_g_1_xoffThrd_f - DsIrmPortFlowControlThrdProfile_g_0_xoffThrd_f;
        for (index1 = 0; index1 < 8; index1++)
        {
            SetDsIrmPortFlowControlThrdProfile(V, g_0_xoffThrd_f + step * index1, &fc_profile, 256);
            SetDsIrmPortFlowControlThrdProfile(V, g_0_xonThrd_f + step * index1, &fc_profile, 224);

        }
        cmd = DRV_IOW(DsIrmPortFlowControlThrdProfile_t, DRV_ENTRY_FLAG);
        for (index = 0; index < entry_num; index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &fc_profile));
        }

        /*TMM default oobfc/pfc thrd */
        sys_usw_ftm_query_table_entry_num(lchip, DsErmPortFcCfg_t, &entry_num);
        SetDsErmPortFcCfg(V, xoffThrd_f, &ds_egr_port_tc_fc_profile, 256);
        SetDsErmPortFcCfg(V, xonThrd_f, &ds_egr_port_tc_fc_profile,  224);
        cmd = DRV_IOW(DsErmPortFcCfg_t, DRV_ENTRY_FLAG);
        for (index = 0; index < entry_num; index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds_egr_port_tc_fc_profile));
        }
    }
    if (DRV_FROM_AT(lchip))
    {
        ds_t ds;
        sal_memset(&ds, 0, sizeof(ds));
        sys_usw_ftm_query_table_entry_num(lchip, DsQMgrChanGrpMap_t, &entry_num);
        for (index = 0; index < entry_num; index++)
        {
            SetDsQMgrChanGrpMap(V, groupId_f, &ds, index);
            cmd = DRV_IOW(DsQMgrChanGrpMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds));
        }
        sal_memset(&ds, 0, sizeof(ds));
        sys_usw_ftm_query_table_entry_num(lchip, DsQMgrGrpChanMap_t, &entry_num);
        SetDsQMgrGrpChanMap(V, g_0_sel_f, &ds, 1);
        SetDsQMgrGrpChanMap(V, g_1_sel_f, &ds, 1);
        SetDsQMgrGrpChanMap(V, g_2_sel_f, &ds, 1);
        SetDsQMgrGrpChanMap(V, g_3_sel_f, &ds, 1);
        SetDsQMgrGrpChanMap(V, g_4_sel_f, &ds, 1);
        SetDsQMgrGrpChanMap(V, g_5_sel_f, &ds, 1);
        SetDsQMgrGrpChanMap(V, g_6_sel_f, &ds, 1);
        SetDsQMgrGrpChanMap(V, g_7_sel_f, &ds, 1);
        SetDsQMgrGrpChanMap(V, g_8_sel_f, &ds, 1);
        SetDsQMgrGrpChanMap(V, g_9_sel_f, &ds, 1);
        SetDsQMgrGrpChanMap(V, g_10_sel_f, &ds, 1);
        SetDsQMgrGrpChanMap(V, g_11_sel_f, &ds, 1);
        for (index = 0; index < entry_num; index++)
        {
            SetDsQMgrGrpChanMap(V, chanId1_f, &ds, index);
            SetDsQMgrGrpChanMap(V, chanId2_f, &ds, index);
            cmd = DRV_IOW(DsQMgrGrpChanMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds));
        }

        sal_memset(&ds, 0, sizeof(ds));
        //SetDsErmPortTcMbCfg(V, g_0_mbInformEn_f, &erm_porttc_mb, 1);
        //SetDsErmPortTcMbCfg(V, g_1_mbInformEn_f, &erm_porttc_mb, 1);
        /*Default all TC select 3 means disabled*/
        SetDsErmPortTcMbCfg(V, tc_0_mbSel_f, &ds, 3);
        SetDsErmPortTcMbCfg(V, tc_1_mbSel_f, &ds, 3);
        SetDsErmPortTcMbCfg(V, tc_2_mbSel_f, &ds, 3);
        SetDsErmPortTcMbCfg(V, tc_3_mbSel_f, &ds, 3);
        SetDsErmPortTcMbCfg(V, tc_4_mbSel_f, &ds, 3);
        SetDsErmPortTcMbCfg(V, tc_5_mbSel_f, &ds, 3);
        SetDsErmPortTcMbCfg(V, tc_6_mbSel_f, &ds, 3);
        SetDsErmPortTcMbCfg(V, tc_7_mbSel_f, &ds, 3);
        cmd = DRV_IOW(DsErmPortTcMbCfg_t, DRV_ENTRY_FLAG);
        for (index = 0; index < MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM); index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds));
        }
        sal_memset(&ds, 0, sizeof(ds));
        SetErmResrcMonCtl(V, resrcMaxEn_f, &ds, 1);
        SetErmResrcMonCtl(V, resrcShadowUpdateEn_f, &ds, 1);
        SetErmResrcMonCtl(V, trigger_c2cCnt_f, &ds, 0x3FFFF);
        SetErmResrcMonCtl(V, trigger_criticalCnt_f, &ds, 0x3FFFF);
        SetErmResrcMonCtl(V, trigger_scCnt0_f, &ds, 0x3FFFF);
        SetErmResrcMonCtl(V, trigger_scCnt1_f, &ds, 0x3FFFF);
        SetErmResrcMonCtl(V, trigger_scCnt2_f, &ds, 0x3FFFF);
        SetErmResrcMonCtl(V, trigger_scCnt3_f, &ds, 0x3FFFF);
        SetErmResrcMonCtl(V, trigger_totalCnt_f, &ds, 0x3FFFF);
        cmd = DRV_IOW(ErmResrcMonCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        cmd = DRV_IOW(IrmResrcMonCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

        sal_memset(&ds, 0, sizeof(ds));
        SetIrmResrcMonHeadroomCtl(V, trigger_headroomCnt_f, &ds, 0x3FFFF);
        cmd = DRV_IOW(IrmResrcMonHeadroomCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        sal_memset(&ds, 0, sizeof(ds));
        SetErmResrcMonState(V, resrcShadowLock_f, &ds, 0);
        cmd = DRV_IOW(ErmResrcMonState_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        cmd = DRV_IOW(IrmResrcMonState_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

        sal_memset(&ds, 0, sizeof(ds));
        /* Acl Span on drop mode, bit set means only match with acl, bit unset means match with acl or not span packet*/
        cmd = DRV_IOR(IpeFwdReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        field_val = GetIpeFwdReserved(V, reserved_f, ds);
        field_val |= (1<<0);
        SetIpeFwdReserved(V, reserved_f, &ds, field_val);
        cmd = DRV_IOW(IpeFwdReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    }

    return CTC_E_NONE;

}
STATIC int32
_sys_usw_register_init_qos_sch(uint8 lchip)
{
    uint32 cmd                     = 0;
    uint32 chan_id                 = 0;
    uint8  level                   = 0;
    uint16 index = 0;
    uint32 max_size = 0;
    DsQMgrGrpParentSelect_m parent_select;
    DsQMgrCosWfqWeight_m cos_weight;
    DsQMgrQueSchMap_m que_sch_map;
    uint32 weight_table_id[CTC_QOS_SCHED_GROUP_LVL_Q] = {DsQMgrL0ChildWfqWeight_t, DsQMgrL1ChildWfqWeight_t,
                                                       DsQMgrL2ChildWfqWeight_t, DsQMgrL3ChildWfqWeight_t};

    uint32 lvl_grp_num[CTC_QOS_SCHED_GROUP_LVL_Q] = {MCHIP_CAP(SYS_CAP_QOS_L1_GRP_NUM), MCHIP_CAP(SYS_CAP_QOS_L2_GRP_NUM),
                                                   MCHIP_CAP(SYS_CAP_QOS_L3_GRP_NUM), MCHIP_CAP(SYS_CAP_QOS_QUE_GRP_NUM)};
    uint32 lvl_grp_num_tmg[CTC_QOS_SCHED_GROUP_LVL_Q] = {MCHIP_CAP(SYS_CAP_QOS_QUE_GRP_NUM), 0, 0, 0};

    sal_memset(&parent_select, 0, sizeof(DsQMgrGrpParentSelect_m));
    sal_memset(&cos_weight, 0, sizeof(DsQMgrCosWfqWeight_m));
    sal_memset(&que_sch_map, 0, sizeof(DsQMgrQueSchMap_m));

    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    if (DRV_IS_TMG(lchip))
    {
        sal_memcpy(lvl_grp_num, lvl_grp_num_tmg, CTC_QOS_SCHED_GROUP_LVL_Q * sizeof(uint32));
    }

    /*config default grp sch weight*/
    SetDsQMgrL0ChildWfqWeight(V, weight_f, &parent_select, 1);
    for (level = 0; level < CTC_QOS_SCHED_GROUP_LVL_Q; level++)
    {
        cmd = DRV_IOW(weight_table_id[level], DRV_ENTRY_FLAG);
        for (index = 0; index < lvl_grp_num[level]; index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &parent_select));
        }
    }

    /*config default queue sch weight*/
    sys_usw_ftm_query_table_entry_num(lchip, DsQMgrCosWfqWeight_t, &max_size);
    for (index = 0; index < MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_GRP); index++)
    {
        SetDsQMgrCosWfqWeight(V, g_0_weight_f + index, &cos_weight, 1);
    }

    for (index = 0; index < max_size; index++)
    {
        cmd = DRV_IOW(DsQMgrCosWfqWeight_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cos_weight));

        cmd = DRV_IOW(DsQMgrQueWfqWeight0_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cos_weight));

        cmd = DRV_IOW(DsQMgrQueWfqWeight1_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cos_weight));
    }

    /*config queue sch class*/
    if (!DRV_FROM_AT(lchip))
    {
        for (index = 0; index < MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_GRP); index++)
        {
            SetDsQMgrQueSchMap(V, cos_0_nodeSel_f + index, &que_sch_map, index);
        }

        cmd = DRV_IOW(DsQMgrQueSchMap_t, DRV_ENTRY_FLAG);
        for (index = 0; index < MCHIP_CAP(SYS_CAP_QOS_QUE_GRP_NUM); index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &que_sch_map));
        }
    }
    /*dma group*/
    chan_id = MCHIP_CAP(SYS_CAP_CHANID_DMA_RX0);
    cmd = DRV_IOW(DsQMgrL0ParentSelect_t, DsQMgrL0ParentSelect_parentId_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &chan_id));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_register_init_qos_queue(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint16 dest_id = 0;
    uint16 eunit_dest_id_start = 0;
    uint16 eunit_dest_id_end = 0;
    uint16 lport = 0;
    uint32 channel = 0;
    uint32 tbl_id = 0;
    uint16 group_vec = 0;
    uint16 index = 0;
    uint8 step = 0;
    uint16 loop = 0;
    uint8 loop1 = 0;
    uint8  gchip = 0;
    uint8 dp = 0;
    uint32 ctl_que_bmp[8] = {0};
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    ds_t ds;

    /*init drop channel*/
    sal_memset(ds, 0, sizeof(ds));
    SetQWriteRsvChanCtl(V, reservedChannelIdValid_f, ds, 1);
    SetQWriteRsvChanCtl(V, reservedChannelId_f, ds, MCHIP_CAP(SYS_CAP_CHANID_DROP));
    SetQWriteRsvChanCtl(V, g_0_reservedChannelRangeValid_f, ds, 1);
    SetQWriteRsvChanCtl(V, g_0_reservedChannelRangeMax_f, ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
    SetQWriteRsvChanCtl(V, g_0_reservedChannelRangeMin_f, ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
    SetQWriteRsvChanCtl(V, g_1_reservedChannelRangeValid_f, ds, 1);
    SetQWriteRsvChanCtl(V, g_1_reservedChannelRangeMax_f, ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
    SetQWriteRsvChanCtl(V, g_1_reservedChannelRangeMin_f, ds, MCHIP_CAP(SYS_CAP_CHANID_RSV));
    cmd = DRV_IOW(QWriteRsvChanCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    if (DRV_FROM_AT(lchip))
    {
        McQWriteRsvChanCtl_m rsv_chan_ctl;
        cmd = DRV_IOR(McQWriteRsvChanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rsv_chan_ctl));
        SetMcQWriteRsvChanCtl(V, reservedChannelId_f, &rsv_chan_ctl, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetMcQWriteRsvChanCtl(V, reservedChannelIdValid_f, &rsv_chan_ctl, 1);
        SetMcQWriteRsvChanCtl(V, g_0_reservedChannelRangeValid_f, &rsv_chan_ctl, 1);
        SetMcQWriteRsvChanCtl(V, g_0_reservedChannelRangeMax_f, &rsv_chan_ctl, MCHIP_CAP(SYS_CAP_CHANID_DROP));
        SetMcQWriteRsvChanCtl(V, g_0_reservedChannelRangeMin_f, &rsv_chan_ctl, MCHIP_CAP(SYS_CAP_CHANID_DROP));
        SetMcQWriteRsvChanCtl(V, g_1_reservedChannelRangeValid_f, &rsv_chan_ctl, 1);
        SetMcQWriteRsvChanCtl(V, g_1_reservedChannelRangeMax_f, &rsv_chan_ctl, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        SetMcQWriteRsvChanCtl(V, g_1_reservedChannelRangeMin_f, &rsv_chan_ctl, MCHIP_CAP(SYS_CAP_CHANID_RSV));
        cmd = DRV_IOW(McQWriteRsvChanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rsv_chan_ctl));

        cmd = DRV_IOW(UcQWriteRsvChanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rsv_chan_ctl));
    }
    eunit_dest_id_start = MCHIP_CAP(SYS_CAP_CPU_REASON_DEST_ID_BASE_EUNIT);
    eunit_dest_id_end = eunit_dest_id_start + MCHIP_CAP(SYS_CAP_CPU_REASON_GRP_NUM_EUNIT) * MCHIP_CAP(SYS_CAP_CPU_REASON_GRP_Q_NUM_EUNIT);
    /*to cpu, dest id and channel map*/
    for (dest_id = 0; dest_id < MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP); dest_id++)
    {
        /*
         *dest id:0   -  127, dma channel, sub queue id enq
         *dest id:128 -  143, dma channel, group+priority enq
         *dest id:144 -  159, dma channel, group + priority enq for c2c pkt
         *dest id:192, cpu mac channel0
         *dest id:208, cpu mac channel1
         *dest id:224, cpu mac channel2
         *dest id:240, cpu mac channel3
         *from tm, 4 dma chan
         *dest id:128-131, from tm, group+priority enq(0-3)
         *dest id:164-167, from tm, group+priority enq(4-7)
         *dest id:200-203, from tm, group+priority enq(8-11)
         *dest id:236-239, from tm, group+priority enq(12-15)
         *from tm, 2 dma chan
         *dest id:128-135, from tm, group+priority enq(0-7)
         *dest id:200-207, from tm, group+priority enq(8-15)
         */
        if ((dest_id == (SYS_ENCODE_DESTMAP_CPU_MAC(0, 0) & 0xFF))
            ||(dest_id == (SYS_ENCODE_DESTMAP_CPU_MAC(0, 1) & 0xFF))
            ||(dest_id == (SYS_ENCODE_DESTMAP_CPU_MAC(0, 2) & 0xFF))
            ||(dest_id == (SYS_ENCODE_DESTMAP_CPU_MAC(0, 3) & 0xFF)))/* refer to SYS_ENCODE_DESTMAP_CPU_MAC*/
        {
               uint32 cpu_mac_channel[SYS_USW_CPU_MAC_NUM] = {MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC0), MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC1),
                                                              MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC2), MCHIP_CAP(SYS_CAP_CHANID_CPU_MAC3)};
               channel = cpu_mac_channel[SYS_DESTMAP_TO_CPU_MAC(dest_id)];
        }
        else
        {
            channel = MCHIP_CAP(SYS_CAP_CHANID_DMA_RX0);
        }
        if (DRV_FROM_AT(lchip))
        {
            DsIpeFwdDestSubQueMap_m fwd_subQ_map;
            DsMcQWriteDestSubQueMap_m mcsubQ_map;
            sal_memset(&fwd_subQ_map, 0, sizeof(fwd_subQ_map));
            sal_memset(&mcsubQ_map, 0, sizeof(mcsubQ_map));
            if (dest_id >= eunit_dest_id_start && dest_id < eunit_dest_id_end)/*only at*/
            {
                channel = MCHIP_CAP(SYS_CAP_CHANID_EUNIT0) + (dest_id - eunit_dest_id_start) / MCHIP_CAP(SYS_CAP_CPU_REASON_GRP_Q_NUM_EUNIT);
            }
            SetDsIpeFwdDestSubQueMap(V, ppDestPort_f, &fwd_subQ_map, channel);
            SetDsMcQWriteDestSubQueMap(V, ppDestPort_f, &mcsubQ_map, channel);
            cmd = DRV_IOW(DsIpeFwdDestSubQueMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, dest_id, cmd, &fwd_subQ_map));
            cmd = DRV_IOW(DsMcQWriteDestSubQueMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, dest_id, cmd, &mcsubQ_map));
        }
        else
        {
            cmd = DRV_IOW(DsIpeFwdSubQueChannelMap_t, DsIpeFwdSubQueChannelMap_channelId_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, dest_id, cmd, &channel));
            cmd = DRV_IOW(DsQWriteSubQueChannelMap_t, DsQWriteSubQueChannelMap_channelId_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, dest_id, cmd, &channel));
        }
    }

    /*port channel map*/
    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));
    lport = DRV_FROM_AT(lchip)?MCHIP_CAP(SYS_CAP_PORT_NUM):0;
    for (; lport < MCHIP_CAP(SYS_CAP_PORT_NUM); lport++)
    {
        dmps_port_info.gport = CTC_MAP_LPORT_TO_GPORT(gchip, lport);
#if (SDK_WORK_PLATFORM == 0) && (0 == SDK_WORK_ENV)
{
        uint32 port_type = 0;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, (void *)&port_type));
        if (SYS_DMPS_RSV_PORT == port_type)
        {
            channel = MCHIP_CAP(SYS_CAP_CHANID_DROP);
        }
        else
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel));
        }
}
#else
        if (lport < SYS_RSV_PORT_START)
        {
            channel = lport;
        }
        else
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel));
        }
#endif

        field_val = SYS_USW_CHANNEL_ENCODE(channel);
        cmd = DRV_IOW(DsQWriteDestPortChannelMap_t, DsQWriteDestPortChannelMap_channelId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));

        cmd = DRV_IOW(DsDestPortChannelMap_t, DsDestPortChannelMap_channelId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));
    }

    /*config QWriteCtl*/
    field_val = DRV_IS_TMG(lchip) ? MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_NETWORK_MISC) : MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_NETWORK_MISC) >> 10;
    cmd = DRV_IOR(QWriteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetQWriteCtl(V, level0HashType_f, &ds, 0);
    SetQWriteCtl(V, level1HashType_f, &ds, 1);
    SetQWriteCtl(V, level2HashType_f, &ds, 2);
    SetQWriteCtl(V, useLogicDestPort_f, &ds, 0);
    SetQWriteCtl(V, g_0_queueBase_f, &ds, field_val);
    SetQWriteCtl(V, g_1_queueBase_f, &ds, field_val);
    SetQWriteCtl(V, g_2_queueBase_f, &ds, field_val);
    SetQWriteCtl(V, g_3_queueBase_f, &ds, field_val);
    SetQWriteCtl(V, g_4_queueBase_f, &ds, field_val);
    SetQWriteCtl(V, g_5_queueBase_f, &ds, field_val);
    SetQWriteCtl(V, g_6_queueBase_f, &ds, field_val);
    SetQWriteCtl(V, g_7_queueBase_f, &ds, field_val);
    SetQWriteCtl(V, cpuPacketQueMapType_f, &ds, 3);
    SetQWriteCtl(V, unkownPacketQueMapType_f, &ds, 1);
    SetQWriteCtl(V, knownMcPacketQueMapType_f, &ds, 1);
    SetQWriteCtl(V, spanPacketQueMapType_f, &ds, 2);
    SetQWriteCtl(V, cpuFwdPacketQueMapType_f, &ds, 4);
    SetQWriteCtl(V, c2cPacketQueMapType_f, &ds, 5);
    SetQWriteCtl(V, spanToCpuQueueEn_f, &ds, 0x2);/*bit0:to remote chip,bit1:to local chip*/
    cmd = DRV_IOW(QWriteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(QMgrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetQMgrCtl(V, netCtlQueBase_f, &ds, field_val);
    cmd = DRV_IOW(QMgrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    /*BEGIN:queue depth for int*/
    sal_memset(ds, 0, sizeof(ds));
    sal_memset(&ctl_que_bmp, 0xff, sizeof(ctl_que_bmp));
    cmd = DRV_IOR(EpePktProcQueBaseCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetEpePktProcQueBaseCtl(V, ctlQueueBase_f, &ds, field_val);
    SetEpePktProcQueBaseCtl(A, ctlQueueIntEn_f, &ds, ctl_que_bmp);
    cmd = DRV_IOW(EpePktProcQueBaseCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    sal_memset(ds, 0, sizeof(ds));
    for (index = 0; index < MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_EXCP) / MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_CHAN); index++)
    {
        SetDsQueueIdBase(V, grpOffsetValid_f, &ds, 1);
        cmd = DRV_IOW(DsQueueIdBase_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds));
    }
    /*END:queue depth for int*/

    field_val = 0x3FFF;
    cmd = DRV_IOW(EpeHdrAdjSpanCtl_t, EpeHdrAdjSpanCtl_spanOnDropRsvQueId_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    /*config queue group select dma ring*/
    sal_memset(ds, 0, sizeof(ds));
    step = EpeHdrEditToDmaCtl_g_1_dmaChanId_f - EpeHdrEditToDmaCtl_g_0_dmaChanId_f;
    for (loop = 0; loop < 16; loop++)
    {
        SetEpeHdrEditToDmaCtl(V, g_0_dmaChanId_f + step * loop, &ds, loop / 4);
    }
    SetEpeHdrEditToDmaCtl(V, lxGrpBaseMin_f, &ds, MCHIP_CAP(SYS_CAP_CHANNEL_NUM));
    SetEpeHdrEditToDmaCtl(V, lxGrpBaseMax_f, &ds, MCHIP_CAP(SYS_CAP_CHANNEL_NUM) + 16);
    SetEpeHdrEditToDmaCtl(V, lxSel_f, &ds, 0);
    cmd = DRV_IOW(EpeHdrEditToDmaCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    /*config dma flow control*/
    sal_memset(ds, 0, sizeof(ds));
    step = DmaRxStallMap_g_1_queGrpVec_f - DmaRxStallMap_g_0_queGrpVec_f;
    for (loop = 0; loop < 4; loop++)
    {
        group_vec = 0;
        for (loop1 = 0; loop1 < 4; loop1++)
        {
            CTC_BIT_SET(group_vec, 4 * loop + loop1);
        }
        SetDmaRxStallMap(V, g_0_queGrpVec_f + step * loop, &ds, group_vec);
    }
    cmd = DRV_IOW(DmaRxStallMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    /*set flowctl cos remap*/
    sal_memset(ds, 0, sizeof(ds));
    step = DsQMgrFlowCtlMap0_cos_1_sel_f - DsQMgrFlowCtlMap0_cos_0_sel_f;
    for (loop = 0; loop < MCHIP_CAP(SYS_CAP_QOS_QUE_GRP_NODE_NUM); loop++)
    {
        SetDsQMgrFlowCtlMap0(V, cos_0_sel_f + step * loop, &ds, loop);
    }
    for (dp = 0; dp < 2; dp++)
    {
        tbl_id = dp == 0 ? DsQMgrFlowCtlMap0_t : DsQMgrFlowCtlMap1_t;
        for (loop = 0; loop < MCHIP_CAP(SYS_CAP_PER_DP_PHY_CHANNEL_NUM); loop++)
        {
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, loop, cmd, &ds));
        }
    }

    /*set oobfc cos remap*/
    step = DsQMgrOobFcMap_cos_1_sel_f - DsQMgrOobFcMap_cos_0_sel_f;
    for(loop = 0; loop < 32; loop++)
    {
        for (loop1 = 0; loop1 < 8; loop1++)
        {
            field_val = loop1;
            cmd = DRV_IOW(DsQMgrOobFcMap_t, DsQMgrOobFcMap_cos_0_sel_f + loop1 * step);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, loop, cmd, &field_val));
        }
    }
    return CTC_E_NONE;
}
STATIC int32
_sys_usw_register_init_qos(uint8 lchip)
{
    CTC_ERROR_RETURN(_sys_usw_register_init_qos_queue(lchip));
    CTC_ERROR_RETURN(_sys_usw_register_init_qos_sch(lchip));
    CTC_ERROR_RETURN(_sys_usw_register_init_qos_resrc(lchip));
    return CTC_E_NONE;
}

int32
_sys_usw_register_init_xpipe(uint8 lchip)
{
    /* initialize priority+color and queue map type default go through low priority channel */
    ds1_t ds = {0};
    uint32 cmd = 0;
    uint32 tmp[3] = {0, 0, 0xfffff};
    uint16 index = 0;
    uint8 tmp_lchip =lchip;

    if (DRV_FROM_AT(lchip))
    {
        sys_port_info_t port_info;
        uint32 gport = 0;
        uint16 lport = 0;
        uint8  gchip = 0;
        uint8  step  = IpeHeaderAdjustChannelPortMap_g_1_srcGuaranteeEn_f - IpeHeaderAdjustChannelPortMap_g_0_srcGuaranteeEn_f;

        sys_usw_get_gchip_id(lchip, &gchip);

        for (lport = 0; lport < MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP); lport++)
        {
            gport = CTC_MAP_LPORT_TO_GPORT(gchip, lport);
            if (!SYS_GPORT_IS_NETWORK_PORT(gport))
            {
                continue;
            }
            CTC_ERROR_RETURN(sys_usw_port_api_get_com_info(lchip, lport, 0, &port_info));

            tmp_lchip = lchip + port_info.pp_id;
            index  = (port_info.dp_id << 5) | (port_info.sub_chan_id);

            cmd = DRV_IOR(IpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(tmp_lchip, (index & 0x1F), DRV_CMD_PP_EN(cmd), &ds));
            SetIpeHeaderAdjustChannelPortMap(V, g_0_srcGuaranteeEn_f + step * ((index>>5)&0x3), ds, 1);
            cmd = DRV_IOW(IpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(tmp_lchip, (index & 0x1F), DRV_CMD_PP_EN(cmd), &ds));
        }
    }
    else
    {
        cmd = DRV_IOW(QWriteGuaranteeCtl_t, DRV_ENTRY_FLAG);
        if (DRV_IS_TSINGMA(lchip))
        {
            SetQWriteGuaranteeCtl(A, srcGuaranteeEn_f, ds, tmp);
        }
        SetQWriteGuaranteeCtl(A, prioGuaranteeEn_f, ds, tmp);
        SetQWriteGuaranteeCtl(V, pktGuaranteeEn_f, ds, tmp[0]);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    }
    return CTC_E_NONE;
}

int32
sys_usw_register_reset_hw_cb(uint8 lchip, void* user_param)
{
    if (DRV_FROM_TMM(lchip))
    {
        CTC_ERROR_RETURN(_sys_usw_register_init_module(lchip));
    }

    return CTC_E_NONE;
}

int32
sys_usw_register_init(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 val = 0;
    uint32 master_size = sizeof(sys_register_master_t);
    ds1_t ds;
    if (p_usw_register_master[lchip])
    {
        return CTC_E_NONE;
    }

    SYS_VCHIP_MASTER_INIT(lchip, p_usw_register_master, CTC_FEATURE_REGISTER);

    master_size += sizeof(sal_systime_t) * CTC_FEATURE_MAX * drv_vchip_get_pp_num(lchip);
    p_usw_register_master[lchip] = mem_malloc(MEM_SYSTEM_MODULE, master_size);
    if (NULL == p_usw_register_master[lchip])
    {
        return CTC_E_NO_MEMORY;
    }

    sal_memset(p_usw_register_master[lchip], 0, master_size);
    p_usw_register_master[lchip]->wb_last_time = (void*)p_usw_register_master[lchip] + sizeof(sys_register_master_t);

    sal_mutex_create(&p_usw_register_master[lchip]->register_mutex);
    if (NULL == p_usw_register_master[lchip]->register_mutex)
    {
        return CTC_E_NO_MEMORY;
    }
    p_usw_register_master[lchip]->sid_edit_mode = 1;
    if (DRV_FROM_TMM(lchip))
    {
        CTC_ERROR_RETURN(_sys_usw_register_init_module(lchip));
    }
    CTC_ERROR_RETURN(sys_usw_register_chip_init(lchip));
    CTC_ERROR_RETURN(_sys_usw_register_cethertype_spool_init(lchip));

    CTC_ERROR_RETURN(_sys_usw_register_tcat_prof_init(lchip));

    CTC_ERROR_RETURN(_sys_usw_discard_type_init(lchip));

    CTC_ERROR_RETURN(_sys_usw_lkp_ctl_init(lchip));

    CTC_ERROR_RETURN(_sys_usw_misc_ctl_init(lchip));

    /* mpls */
    CTC_ERROR_RETURN(_sys_usw_mpls_ctl_init(lchip));

    /* exception */
    CTC_ERROR_RETURN(_sys_usw_excp_ctl_init(lchip));

    /* ipe loopback hdr adjust ctl */
    CTC_ERROR_RETURN(_sys_usw_ipe_loopback_hdr_adjust_ctl_init(lchip));

    /* ipe route ctl */
    CTC_ERROR_RETURN(_sys_usw_ipe_route_ctl_init(lchip));

    /* ipe brige ctl */
    CTC_ERROR_RETURN(_sys_usw_ipe_brg_ctl_init(lchip));

    /* ipe fwd ctl */
    CTC_ERROR_RETURN(_sys_usw_ipe_fwd_ctl_init(lchip));

    CTC_ERROR_RETURN(_sys_usw_ipe_arp_ctl_init(lchip));

    /* buf retrive ctl , now only process slice0 TODO slice1*/
    CTC_ERROR_RETURN(_sys_usw_buffer_retrieve_ctl_init(lchip));

    /* Ipg init */
    CTC_ERROR_RETURN(_sys_usw_ipg_init(lchip));

	/* lengthAdjust init */
	CTC_ERROR_RETURN(_sys_usw_qmgr_ctl_init(lchip));

    if(DRV_IS_AT(lchip))
    {
        /* ptp init */
        CTC_ERROR_RETURN(_sys_usw_ptp_ctl_init(lchip, 0));
        drv_ser_register_hw_reset_cb(lchip, DRV_SER_HW_RESET_CB_TYPE_PTP, sys_usw_ptp_reset_hw);
    }

    /*init bufferstoreCpuRxLogChannelMap*/
    CTC_ERROR_RETURN(_sys_usw_bufferstoreCpuRxLogChannelMap_init(lchip));

    CTC_ERROR_RETURN(sys_usw_wb_sync_register_cb(lchip, CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MAX,sys_usw_register_wb_sync));

    if(SYS_USW_DMPS_IS_OLD_DB(lchip))
    {
        CTC_ERROR_RETURN(sys_usw_wb_sync_register_cb(lchip, CTC_FEATURE_DATAPATH,SYS_WB_APPID_DATAPATH_SUBID_MAX, sys_usw_datapath_wb_sync));
    }
    CTC_ERROR_RETURN(drv_ser_register_hw_reset_cb(lchip, DRV_SER_HW_RESET_CB_TYPE_REGISTER, sys_usw_register_reset_hw_cb));

    if (CTC_WB_ENABLE(lchip) && (CTC_WB_STATUS(lchip) == CTC_WB_STATUS_RELOADING))
    {
        CTC_ERROR_RETURN(sys_usw_register_wb_restore(lchip));
    }
    if (CTC_WB_ENABLE(lchip))
    {
        CTC_ERROR_RETURN(_sys_usw_register_wb_init(lchip));
    }

    if ((SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) && DRV_IS_TSINGMA(lchip))
    {
        PbCtlScrambleDebugCtl_m scrambledebugctl;
        MCHIP_CAP(SYS_CAP_L4_USER_UDP_TYPE_VXLAN) = 13;

        cmd = DRV_IOR(EpeHdrProcReserved_t, EpeHdrProcReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        val |= (1<<2);
        val |= (1<<3);
        val |= (1<<4);
        val |= (1<<5);
        cmd = DRV_IOW(EpeHdrProcReserved_t, EpeHdrProcReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));

        cmd = DRV_IOR(IpePktProcReserved_t, IpePktProcReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        val |= (1<<0);
        val |= (1<<2);
        val |= (1<<3);
        val |= (1<<4);
        val |= (1<<5);
        val |= (0xf << 6);
        cmd = DRV_IOW(IpePktProcReserved_t, IpePktProcReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));

        cmd = DRV_IOR(IpeAclReserved_t, IpeAclReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        val |= (1<<9);
        val |= (1<<10);
        /*for bug 118377*/
        val |= (1<<11);
        cmd = DRV_IOW(IpeAclReserved_t, IpeAclReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));

        cmd = DRV_IOR(IpeHdrAdjReserved_t, IpeHdrAdjReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        val |= (1<<0);
        cmd = DRV_IOW(IpeHdrAdjReserved_t, IpeHdrAdjReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));

        cmd = DRV_IOR(EpeHdrEditReserved_t, EpeHdrEditReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        val |= (1<<2);
        cmd = DRV_IOW(EpeHdrEditReserved_t, EpeHdrEditReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));

        cmd = DRV_IOR(IpeLkupMgrReserved_t, IpeLkupMgrReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        val |= (1<<1);
        cmd = DRV_IOW(IpeLkupMgrReserved_t, IpeLkupMgrReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));

        cmd = DRV_IOR(IpeFwdReserved_t, IpeFwdReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        /*for bug 115686*/
        CTC_BIT_UNSET(val, 1);
        val |= (1<<9);
        cmd = DRV_IOW(IpeFwdReserved_t, IpeFwdReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));

        cmd = DRV_IOR(MetFifoReserved_t, MetFifoReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        val |= (1<<2);
        cmd = DRV_IOW(MetFifoReserved_t, MetFifoReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));

        cmd = DRV_IOR(BufRetrvReserved_t, BufRetrvReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        val |= (1<<0);
        cmd = DRV_IOW(BufRetrvReserved_t, BufRetrvReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));

        /* TM1.1 twamp reflector support light mode */
        sal_memset(ds, 0 ,sizeof(ds));
        cmd = DRV_IOR(OamFwdReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        val = GetOamFwdReserved(V, reserved_f, ds);
        val |= (1<<0);
        SetOamFwdReserved(V, reserved_f, ds, val);
        cmd = DRV_IOW(OamFwdReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

        sal_memset(&scrambledebugctl, 0, sizeof(scrambledebugctl));
        SetPbCtlScrambleDebugCtl(V, hash2DebugEn_f, &scrambledebugctl, 1);
        SetPbCtlScrambleDebugCtl(V, hash3DebugEn_f, &scrambledebugctl, 1);
        cmd = DRV_IOW(PbCtlScrambleDebugCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &scrambledebugctl));
    }

    if (((SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) && DRV_IS_TMM(lchip)) || DRV_IS_TMG(lchip))
    {
        uint32 u32_val=0;
        IpeAclReserved_m ipe_aclresv;
        IpeHdrAdjReserved_m ipe_hdradjresv;
        FlowAccIpeReserved_m flow_acciperesv;
        IpeFwdReserved_m     ipe_fwdresv;
        EpeHdrAdjReserved_m  epe_hdradjresv;
        EpeHdrEditReserved_m epe_hdreditresv;

        cmd = DRV_IOR(IpeHdrAdjReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_hdradjresv));
        u32_val = GetIpeHdrAdjReserved(V, reserved_f, &ipe_hdradjresv);
        u32_val |= (0x07 << 11 );
        SetIpeHdrAdjReserved(V, reserved_f, &ipe_hdradjresv, u32_val);
        cmd = DRV_IOW(IpeHdrAdjReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_hdradjresv));

        cmd = DRV_IOR(IpeFwdReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwdresv));
        u32_val = GetIpeFwdReserved(V, reserved_f, &ipe_fwdresv);
        u32_val |= 0x0D;
        SetIpeFwdReserved(V, reserved_f, &ipe_fwdresv, u32_val);
        cmd = DRV_IOW(IpeFwdReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwdresv));

        cmd = DRV_IOR(EpeHdrAdjReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_hdradjresv));
        u32_val = GetEpeHdrAdjReserved(V, reserved_f, &epe_hdradjresv);
        u32_val |= (0x1F << 3);
        u32_val |= (0x1 << 8);
        SetEpeHdrAdjReserved(V, reserved_f, &epe_hdradjresv, u32_val);
        cmd = DRV_IOW(EpeHdrAdjReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_hdradjresv));

        cmd = DRV_IOR(EpeHdrEditReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_hdreditresv));
        u32_val = GetEpeHdrEditReserved(V, reserved_f, &epe_hdreditresv);
        u32_val |= (0x1F << 1);
        u32_val |= (0x1 << 6);
        SetEpeHdrEditReserved(V, reserved_f, &epe_hdreditresv, u32_val);
        cmd = DRV_IOW(EpeHdrEditReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &epe_hdreditresv));

        cmd = DRV_IOR(FlowAccIpeReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &flow_acciperesv));
        u32_val = GetFlowAccIpeReserved(V, reserved_f, &flow_acciperesv);
        u32_val |= (0x1);
        SetFlowAccIpeReserved(V, reserved_f, &flow_acciperesv, u32_val);
        cmd = DRV_IOW(FlowAccIpeReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &flow_acciperesv));

        cmd = DRV_IOR(IpeAclReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_aclresv));
        u32_val = GetIpeAclReserved(V, reserved_f, &ipe_aclresv);
        u32_val |= 0x3;
        SetIpeAclReserved(V, reserved_f, &ipe_aclresv, u32_val);
        cmd = DRV_IOW(IpeAclReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_aclresv));
    }
    if (DRV_FROM_AT(lchip))
    {
        sal_memset(ds, 0 ,sizeof(ds));
        SetEpeScheduleTruncateCheckCfg(V, cfgMiscTruncateCheckEn_f, ds, 1);
        cmd = DRV_IOW(EpeScheduleTruncateCheckCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    }
    else if ((DRV_IS_TMM(lchip) && (SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_C)) || DRV_IS_TMG(lchip))
    {
        sal_memset(ds, 0 ,sizeof(ds));
        MCHIP_CAP(SYS_CAP_PKT_TRUNCATED_LEN) = 1023;
        SetEpeScheduleTruncateCheckCfg(V, cfgDma0TruncateCheckEn_f, ds, 1);
        SetEpeScheduleTruncateCheckCfg(V, cfgDma1TruncateCheckEn_f, ds, 1);
        SetEpeScheduleTruncateCheckCfg(V, cfgCpuMac0TruncateCheckEn_f, ds, 1);
        SetEpeScheduleTruncateCheckCfg(V, cfgCpuMac1TruncateCheckEn_f, ds, 1);
        cmd = DRV_IOW(EpeScheduleTruncateCheckCfg_t, DRV_ENTRY_FLAG);
        SYS_SET_TBL_ALL_DP(lchip, cmd, ds);
    }

    cmd = DRV_IOR(IpeIntfMapperCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    val = GetIpeIntfMapperCtl(V, layer4SecurityCheckEn_f, ds);
    val |= 0x1;
    SetIpeIntfMapperCtl(V, layer4SecurityCheckEn_f, ds, val);
    cmd = DRV_IOW(IpeIntfMapperCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    CTC_ERROR_RETURN(_sys_usw_register_init_qos(lchip));
    CTC_ERROR_RETURN(_sys_usw_register_init_nexthop(lchip));
    CTC_ERROR_RETURN(_sys_usw_register_init_l3(lchip));
    CTC_ERROR_RETURN(_sys_usw_register_init_xpipe(lchip));
#if (FEATURE_MODE == 0)
#if defined E_UNIT && (FEATURE_MODE == 0)
    CTC_ERROR_RETURN(sys_usw_eunit_init(lchip));
    drv_ser_register_hw_reset_cb(lchip, DRV_SER_HW_RESET_CB_TYPE_EUNIT, sys_usw_eunit_hw_reset);
#endif
#endif
#if (FEATURE_MODE == 0)
    if(DRV_IS_TSINGMA(lchip) && (SDK_WORK_PLATFORM == 0) && (!(CTC_WB_ENABLE(lchip) && CTC_WB_STATUS(lchip) == CTC_WB_STATUS_RELOADING)))
    {
        CTC_ERROR_RETURN(_sys_usw_tcam_bist_check(lchip));
    }
#endif
    sys_usw_mchip_set_feature_en(lchip,CTC_FEATURE_REGISTER);
    return CTC_E_NONE;
}

int32
sys_usw_register_deinit(uint8 lchip)
{
    LCHIP_CHECK(lchip);

    CTC_ERROR_RETURN(sys_usw_common_deinit(lchip));
    if (NULL == p_usw_register_master[lchip])
    {
        return CTC_E_NONE;
    }
    SYS_VCHIP_MASTER_DEINIT(lchip, p_usw_register_master, CTC_FEATURE_REGISTER);

    /*free cethertype_spool node */
    ctc_spool_free(p_usw_register_master[lchip]->cethertype_spool);

    /*opf free*/
    sys_usw_opf_deinit(lchip, p_usw_register_master[lchip]->opf_type_cethertype);


    sal_mutex_destroy(p_usw_register_master[lchip]->register_mutex);

    mem_free(p_usw_register_master[lchip]);

#if (FEATURE_MODE == 0)
#if defined E_UNIT && (FEATURE_MODE == 0)
    sys_usw_eunit_deinit(lchip);
#endif
#endif
    return CTC_E_NONE;
}

int32
sys_usw_register_add_compress_ether_type(uint8 lchip, uint16 new_ether_type, uint16 old_ether_type,uint8* o_cether_type, uint8* o_cether_type_index)
{
    uint32 cmd = 0;
    EtherTypeCompressCam_m    cam_cethertype;
    sys_register_cethertype_t new_cethertype_t = {0};
    sys_register_cethertype_t old_cethertype_t = {0};
    sys_register_cethertype_t*    pcether_get  = NULL;

    new_cethertype_t.ether_type = new_ether_type;
    new_cethertype_t.index.index = *o_cether_type_index;
    old_cethertype_t.ether_type = old_ether_type;

    SYS_REGISTER_INIT_CHECK;

    SYS_USW_REGISTER_LOCK(lchip);
    CTC_ERROR_RETURN_WITH_UNLOCK(ctc_spool_add(p_usw_register_master[lchip]->cethertype_spool,&new_cethertype_t,&old_cethertype_t, &pcether_get), p_usw_register_master[lchip]->register_mutex);
    SYS_USW_REGISTER_UNLOCK(lchip);

    if(o_cether_type)
    {
        *o_cether_type = (1 << 6 | (pcether_get->index.index&0x3F));
        sal_memset(&cam_cethertype, 0,sizeof(cam_cethertype));
        SetEtherTypeCompressCam(V, etherType_f, &cam_cethertype, pcether_get->ether_type);
        SetEtherTypeCompressCam(V, compressEtherType_f, &cam_cethertype, pcether_get->index.index);
        SetEtherTypeCompressCam(V, valid_f, &cam_cethertype, 1);

        cmd = DRV_IOW(EtherTypeCompressCam_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, pcether_get->index.index, cmd, &cam_cethertype));
    }
        *o_cether_type_index = pcether_get->index.index&0x3F;

    return CTC_E_NONE;
}

int32
sys_usw_register_remove_compress_ether_type(uint8 lchip, uint8 ether_type_index)
{
    uint16 ether_type = 0;
    uint32 cmd = 0;
    sys_register_cethertype_t cethertype_t = {0};
    EtherTypeCompressCam_m cam_cethertype;

    SYS_REGISTER_INIT_CHECK;

    sal_memset(&cam_cethertype, 0 , sizeof(ProgramAclEtherTypeCompressor_m));

    cmd = DRV_IOR(EtherTypeCompressCam_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, ether_type_index, DRV_CMD_PP_EN(cmd), &cam_cethertype));
    ether_type = GetEtherTypeCompressCam(V,etherType_f, &cam_cethertype);

    cethertype_t.ether_type = ether_type;

    SYS_USW_REGISTER_LOCK(lchip);
    CTC_ERROR_RETURN_WITH_UNLOCK(ctc_spool_remove(p_usw_register_master[lchip]->cethertype_spool, &cethertype_t, NULL), p_usw_register_master[lchip]->register_mutex);
    SYS_USW_REGISTER_UNLOCK(lchip);

    return CTC_E_NONE;
}

const char *_sys_get_feature_desc(int32 feature)
{
    switch(feature)
    {
     case CTC_FEATURE_PORT:
        return "Port";
     case CTC_FEATURE_VLAN:
        return "Vlan";
     case CTC_FEATURE_LINKAGG:
        return "Linkagg";
     case CTC_FEATURE_CHIP:
         return "Chip";
     case CTC_FEATURE_FTM:
         return "FTM";
     case CTC_FEATURE_NEXTHOP:
        return "Nexthop";
     case CTC_FEATURE_L2:
        return "L2";
     case CTC_FEATURE_L3IF:
        return "L3IF";
     case CTC_FEATURE_IPUC:
        return "IPUC";
     case CTC_FEATURE_IPMC:
        return "IPMC";
     case CTC_FEATURE_IP_TUNNEL:
        return "IP_Tunnel";
     case CTC_FEATURE_SCL:
        return "SCL";
     case CTC_FEATURE_ACL:
        return "ACL";
     case CTC_FEATURE_QOS:
        return "Qos";
     case CTC_FEATURE_SECURITY:
        return "Security";
     case CTC_FEATURE_STATS:
        return "Stats";
     case CTC_FEATURE_MPLS:
        return "Mpls";
     case CTC_FEATURE_OAM:
         return "OAM";
     case CTC_FEATURE_APS:
         return "APS";
     case CTC_FEATURE_PTP:
         return "PTP";
     case CTC_FEATURE_DMA:
         return "DMA";
     case CTC_FEATURE_INTERRUPT:
         return "Interrupt";
     case CTC_FEATURE_PACKET:
        return "Packet";
     case CTC_FEATURE_PDU:
        return "PDU";
     case CTC_FEATURE_MIRROR:
         return "Mirror";
     case CTC_FEATURE_BPE:
         return "BPE";
     case CTC_FEATURE_STACKING:
         return "Stacking";
     case CTC_FEATURE_OVERLAY:
         return "Overlay";
     case CTC_FEATURE_IPFIX:
         return "IPFIX";
     case CTC_FEATURE_EFD:
         return "EFD";
     case CTC_FEATURE_MONITOR:
        return "Monitor";
     case CTC_FEATURE_FCOE:
        return "FCOE";
     case CTC_FEATURE_TRILL:
        return "TRILL";
     case CTC_FEATURE_WLAN:
        return "WLAN";
     case CTC_FEATURE_NPM:
        return "NPM";
     case CTC_FEATURE_VLAN_MAPPING:
        return "VLAN_Mapping";
     case CTC_FEATURE_DOT1AE:
        return "Dot1AE";
     case CTC_FEATURE_SRV6:
         return "SRv6";
     case CTC_FEATURE_DTEL:
         return "DTEL";
     case CTC_FEATURE_DIAG:
        return "Diag";
     case CTC_FEATURE_SC_OAM:
        return "Sc_OAM";
     case CTC_FEATURE_SYNC_ETHER:
        return "SyncE";
     case CTC_FEATURE_APP_VLAN_PORT:
        return "XGPON";
     case CTC_FEATURE_DATAPATH:
         return "Datapath";
     case CTC_FEATURE_REGISTER:
         return "Register";
     case CTC_FEATURE_FLEXE:
          return "FlexE";
    case CTC_FEATURE_PON:
          return "PON";
    case CTC_FEATURE_XDATA:
        return "XDATA";
          default:
            return "Unknown";
      }

}

int32
_sys_usw_feature_init_show_status(uint8 lchip)
{
    uint8 loop=0;
    uint8 i = 0;
    const char* p_feature_str = NULL;
    const char* feature_en = NULL;
    const char* pp_en = NULL;

    if (DRV_FROM_AT(lchip))
    {
        SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n-------------------------------------------------------------\n");
        SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Vchip id  :%d\n", drv_vchip_get_pp_base(lchip));
        SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Vchip ppBmp :0x%x\n", drv_vchip_get_pp_bmp(lchip));
    }

    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n-------------------------------------------------------------\n");
    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-14s%-8s%-14s%-14s%-8s%-14s\n", "Feature", "Inited", "PP", "Feature", "Inited", "PP");
    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "-------------------------------------------------------------\n");
    for(loop=0;loop<CTC_FEATURE_MAX;loop++)
    {
        if(CTC_FEATURE_APP_VLAN_PORT==loop)
        {
            continue;
        }
        if(CTC_IS_BIT_SET(p_sys_mchip_master[lchip]->feature[loop],SYS_FEATURE_CAP))
        {
            p_feature_str = _sys_get_feature_desc(loop);
            feature_en = "NO";
            pp_en = "NO";
            if ((CTC_IS_BIT_SET(p_sys_mchip_master[lchip]->feature[loop], SYS_FEATURE_EN)))
            {
                feature_en = "YES";
            }
            if ((CTC_IS_BIT_SET(p_sys_mchip_master[lchip]->feature[loop], SYS_FEATURE_PP_EN)))
            {
                pp_en = "YES";
            }
            if (!DRV_FROM_AT(lchip))
            {
                pp_en = "-";
            }
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-14s%-8s%-14s", p_feature_str, feature_en, pp_en);

            i++;
            if (0 == (i % 2))
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n");
            }
        }
    }
    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n-------------------------------------------------------------\n");
    return CTC_E_NONE;
}

int32
_sys_usw_register_show_cethertype_status(uint8 lchip)
{
    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"Cethertype Status:" " %s %u\n","max_count:",p_usw_register_master[lchip]->cethertype_spool->max_count);
    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"                   %s %u\n","used_cout:",p_usw_register_master[lchip]->cethertype_spool->count);
    return CTC_E_NONE;
}

int32
sys_usw_register_sdb_config(uint8 lchip, uint8 op_type, uint8 enable)
{
    SYS_REGISTER_INIT_CHECK;
    if (op_type == 0)
    {
        if (drv_sdb_read_from_hw(lchip, enable))
        {
            return CTC_E_NOT_READY;
        }
    }
    else if (op_type == 1 && !enable)
    {
        drv_sdb_set_stop_store(lchip, TRUE);
    }
    else
    {
        /*
            1.invalid op type
            2.only support disable sdb, sdb only can be enabled when sdk init
        */
        return CTC_E_NOT_SUPPORT;
    }

    return CTC_E_NONE;
}

int32
sys_usw_register_dump_table(uint8 lchip, uint8 type, uint32 tbl_id, char* file)
{
    CTC_MAX_VALUE_CHECK(tbl_id, MaxTblId_t-1);
    CTC_ERROR_RETURN(drv_sdb_dump(lchip, type, tbl_id, file));
    return CTC_E_NONE;
}

int32
sys_usw_register_check_table(uint8 lchip, uint8 type, uint8 recover_en, uint32 tbl_id, char* file)
{
    uint8 lchip_start = 0;
    uint8 lchip_end = 0;
    
    CTC_MAX_VALUE_CHECK(tbl_id, MaxTblId_t-1);
    lchip_start = SYS_PP_BASE(lchip);
    lchip_end = lchip_start + SYS_PP_NUM(lchip);
    for (lchip = lchip_start; lchip < lchip_end; lchip++)
    {
        CTC_ERROR_RETURN(drv_sdb_check(lchip, type, recover_en, tbl_id, file));
    }
    return CTC_E_NONE;
}

int32
sys_usw_register_show_sdb_status(uint8 lchip, uint8 type, char* table_name)
{
    drv_sdb_show_status(lchip, type, table_name);
    return CTC_E_NONE;
}

int32
sys_usw_register_show_sdb_changed_table(uint8 lchip, char* tbl_name, uint32 start_time, uint32 end_time)
{
    drv_sdb_show_changed_table(lchip, tbl_name, start_time, end_time);
    return CTC_E_NONE;
}

int32
sys_usw_register_show_status(uint8 lchip)
{
    int32 ret = CTC_E_NONE;
    SYS_REGISTER_INIT_CHECK;

    SYS_USW_REGISTER_LOCK(lchip);
    _sys_usw_feature_init_show_status(lchip);
    _sys_usw_register_show_cethertype_status(lchip);
#if (FEATURE_MODE == 0 && SDB_MODE != SDB_MEM_MODEL)
#if defined E_UNIT && (FEATURE_MODE == 0)
    if(DRV_FROM_TMM(lchip))
    {
        ret = sys_usw_eunit_show_status(lchip, 0, 0);
    }
#endif
#endif
    SYS_USW_REGISTER_UNLOCK(lchip);


    return ret;
}

STATIC int32
_sys_usw_global_get_chip_capability(uint8 lchip, uint32* p_capability)
{
    uint8 int_en = 0;
    CTC_PTR_VALID_CHECK(p_capability);
    sys_usw_global_get_int_en(lchip, &int_en);

    p_capability[CTC_GLOBAL_CAPABILITY_LOGIC_PORT_NUM] = MCHIP_CAP(SYS_CAP_SPEC_LOGIC_PORT_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_MAX_FID] = MCHIP_CAP(SYS_CAP_SPEC_MAX_FID);
    p_capability[CTC_GLOBAL_CAPABILITY_MAX_VRFID] = MCHIP_CAP(SYS_CAP_SPEC_MAX_VRFID);
    p_capability[CTC_GLOBAL_CAPABILITY_MAX_ACL_LOG_ID] = MCHIP_CAP(SYS_CAP_ACL_IGS_MAX_LOG_ID) - (!!int_en);
    p_capability[CTC_GLOBAL_CAPABILITY_MAX_EACL_LOG_ID] = MCHIP_CAP(SYS_CAP_ACL_EGS_MAX_LOG_ID) - (!!int_en);
    p_capability[CTC_GLOBAL_CAPABILITY_MCAST_GROUP_NUM] = MCHIP_CAP(SYS_CAP_SPEC_MCAST_GROUP_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_VLAN_NUM] = MCHIP_CAP(SYS_CAP_SPEC_VLAN_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_VLAN_RANGE_GROUP_NUM] = MCHIP_CAP(SYS_CAP_SPEC_VLAN_RANGE_GROUP_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_STP_INSTANCE_NUM] = MCHIP_CAP(SYS_CAP_SPEC_STP_INSTANCE_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_LINKAGG_GROUP_NUM] = MCHIP_CAP(SYS_CAP_SPEC_LINKAGG_GROUP_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_LINKAGG_MEMBER_NUM] = MCHIP_CAP(SYS_CAP_SPEC_LINKAGG_MEMBER_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_LINKAGG_DLB_FLOW_NUM] = MCHIP_CAP(SYS_CAP_SPEC_LINKAGG_DLB_FLOW_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_LINKAGG_DLB_MEMBER_NUM] = MCHIP_CAP(SYS_CAP_SPEC_LINKAGG_DLB_MEMBER_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_LINKAGG_DLB_GROUP_NUM] = MCHIP_CAP(SYS_CAP_SPEC_LINKAGG_DLB_GROUP_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ECMP_GROUP_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ECMP_GROUP_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ECMP_MEMBER_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ECMP_MEMBER_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ECMP_DLB_FLOW_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ECMP_DLB_FLOW_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_EXTERNAL_NEXTHOP_NUM] = MCHIP_CAP(SYS_CAP_SPEC_EXTERNAL_NEXTHOP_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_GLOBAL_DSNH_NUM] = MCHIP_CAP(SYS_CAP_SPEC_GLOBAL_DSNH_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_MPLS_TUNNEL_NUM] = MCHIP_CAP(SYS_CAP_SPEC_MPLS_TUNNEL_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ARP_ID_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ARP_ID_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_L3IF_NUM] = MCHIP_CAP(SYS_CAP_SPEC_L3IF_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_OAM_SESSION_NUM] = MCHIP_CAP(SYS_CAP_SPEC_OAM_SESSION_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_NPM_SESSION_NUM] = MCHIP_CAP(SYS_CAP_SPEC_NPM_SESSION_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_APS_GROUP_NUM] = MCHIP_CAP(SYS_CAP_APS_GROUP_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_TOTAL_POLICER_NUM] = MCHIP_CAP(SYS_CAP_SPEC_TOTAL_POLICER_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_POLICER_NUM] = MCHIP_CAP(SYS_CAP_SPEC_POLICER_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_TOTAL_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_TOTAL_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_QUEUE_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_QUEUE_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_POLICER_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_POLICER_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE1_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE1_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE2_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE2_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE3_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE3_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE4_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE4_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE5_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE5_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE6_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE6_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE7_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE7_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE8_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE8_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE9_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE9_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE10_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE10_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE11_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE11_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE12_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE12_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE13_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE13_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE14_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE14_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE15_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE15_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SHARE16_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SHARE16_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL0_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL0_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL1_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL1_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL2_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL2_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL3_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL3_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL4_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL4_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL5_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL5_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL6_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL6_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL7_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL7_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL8_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL8_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL9_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL9_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL10_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL10_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL11_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL11_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL12_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL12_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL13_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL13_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL14_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL14_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL15_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL15_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL16_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL16_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL17_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL17_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL18_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL18_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL19_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL19_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL20_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL20_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL21_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL21_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL22_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL22_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL23_IGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL23_IGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL0_EGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL0_EGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL1_EGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL1_EGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL2_EGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL2_EGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL3_EGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL3_EGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL4_EGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL4_EGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL5_EGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL5_EGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL6_EGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL6_EGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL7_EGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL7_EGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL8_EGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL8_EGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL9_EGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL9_EGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL10_EGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL10_EGS_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL11_EGS_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL11_EGS_STATS_NUM);

    p_capability[CTC_GLOBAL_CAPABILITY_ECMP_STATS_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ECMP_STATS_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ROUTE_MAC_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ROUTE_MAC_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_MAC_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_MAC_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_BLACK_HOLE_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_L2_BLACK_HOLE_ENTRY);
    p_capability[CTC_GLOBAL_CAPABILITY_HOST_ROUTE_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_HOST_ROUTE_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_LPM_ROUTE_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_LPM_ROUTE_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_IPMC_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_IPMC_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_MPLS_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_MPLS_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_TUNNEL_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_TUNNEL_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_L2PDU_L2HDR_PROTO_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_L2PDU_BASED_L2HDR_PTL_ENTRY);
    p_capability[CTC_GLOBAL_CAPABILITY_L2PDU_MACDA_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_L2PDU_BASED_MACDA_ENTRY);
    p_capability[CTC_GLOBAL_CAPABILITY_L2PDU_MACDA_LOW24_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_L2PDU_BASED_MACDA_LOW24_ENTRY);
    p_capability[CTC_GLOBAL_CAPABILITY_L2PDU_L2CP_MAX_ACTION_INDEX] = MCHIP_CAP(SYS_CAP_L2PDU_PER_PORT_ACTION_INDEX);
    p_capability[CTC_GLOBAL_CAPABILITY_L3PDU_L3HDR_PROTO_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_L3PDU_BASED_L3HDR_PROTO);
    p_capability[CTC_GLOBAL_CAPABILITY_L3PDU_L4PORT_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_L3PDU_BASED_PORT);
    p_capability[CTC_GLOBAL_CAPABILITY_L3PDU_IPDA_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_L3PDU_BASED_IPDA);
    p_capability[CTC_GLOBAL_CAPABILITY_L3PDU_MAX_ACTION_INDEX] = MCHIP_CAP(SYS_CAP_L3PDU_ACTION_INDEX);
    p_capability[CTC_GLOBAL_CAPABILITY_SCL_HASH_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SCL_HASH_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SCL1_HASH_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SCL1_HASH_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SCL_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SCL0_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SCL1_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SCL1_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SCL2_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SCL2_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_SCL3_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_SCL3_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL_HASH_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL_HASH_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL0_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL0_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL1_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL1_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL2_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL2_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL3_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL3_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL4_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL4_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL5_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL5_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL6_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL6_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL7_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL7_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL8_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL8_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL9_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL9_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL10_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL10_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL11_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL11_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL12_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL12_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL13_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL13_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL14_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL14_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL15_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL15_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL16_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL16_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL17_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL17_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL18_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL18_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL19_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL19_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL20_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL20_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL21_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL21_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL22_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL22_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL23_IGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL23_IGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL0_EGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL0_EGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL1_EGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL1_EGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL2_EGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL2_EGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL3_EGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL3_EGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL4_EGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL4_EGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL5_EGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL5_EGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL6_EGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL6_EGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL7_EGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL7_EGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL8_EGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL8_EGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL9_EGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL9_EGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL10_EGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL10_EGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_ACL11_EGS_TCAM_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_ACL11_EGS_TCAM_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_CID_PAIR_NUM] = MCHIP_CAP(SYS_CAP_ACL_HASH_CID_KEY)+ MCHIP_CAP(SYS_CAP_ACL_TCAM_CID_PAIR);
    p_capability[CTC_GLOBAL_CAPABILITY_UDF_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_ACL_UDF_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_DOT1AE_SC_NUM] = MCHIP_CAP(SYS_CAP_DOT1AE_SEC_CHAN_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_IPFIX_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_IPFIX_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_EFD_FLOW_ENTRY_NUM] = MCHIP_CAP(SYS_CAP_SPEC_EFD_FLOW_ENTRY_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_MAX_LCHIP_NUM] = MCHIP_CAP(SYS_CAP_SPEC_MAX_LCHIP_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_MAX_PHY_PORT_NUM] = MCHIP_CAP(SYS_CAP_SPEC_MAX_PHY_PORT_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_MAX_PORT_NUM] = MCHIP_CAP(SYS_CAP_SPEC_MAX_PORT_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_MAX_CHIP_NUM] = MCHIP_CAP(SYS_CAP_SPEC_MAX_CHIP_NUM);
    p_capability[CTC_GLOBAL_CAPABILITY_PKT_HDR_LEN] = SYS_USW_PKT_HEADER_LEN;

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_global_ctl_l4_check_en(uint8 lchip, ctc_global_control_type_t type, bool* value, uint8 is_set)
{
    uint32 field_val = 0;
    uint32 cmd = 0;
    uint8 bit = 0;

    switch (type)
    {
        case CTC_GLOBAL_DISCARD_TCP_SYN_0_PKT:
            bit = 0;
            break;
        case CTC_GLOBAL_DISCARD_TCP_NULL_PKT:
            bit = 1;
            break;
        case CTC_GLOBAL_DISCARD_TCP_XMAS_PKT:
            bit = 2;
            break;
        case CTC_GLOBAL_DISCARD_TCP_SYN_FIN_PKT:
            bit = 3;
            break;
        case CTC_GLOBAL_DISCARD_SAME_L4_PORT_PKT:
            bit = 4;
            break;
        case CTC_GLOBAL_DISCARD_ICMP_FRAG_PKT:
            bit = 5;
            break;
        default:
            return CTC_E_NOT_SUPPORT;
    }

    cmd = DRV_IOR(IpeIntfMapperCtl_t, IpeIntfMapperCtl_layer4SecurityCheckEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    if (is_set)
    {
        if (*value)
        {
            CTC_BIT_SET(field_val, bit);
        }
        else
        {
            CTC_BIT_UNSET(field_val, bit);
        }
        cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_layer4SecurityCheckEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    }
    else
    {
        *value = CTC_IS_BIT_SET(field_val, bit)? TRUE : FALSE;
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_global_get_panel_ports(uint8 lchip, ctc_global_panel_ports_t* phy_info)
{
#if (SDB_MEM_MODEL == SDB_MODE)
    return CTC_E_NONE;
#endif
    uint16 lport = 0;
    uint16 count = 0;
    int32 ret = 0;
    uint8 gchip = 0;
    uint32 port_type = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));
    for (lport = 0; lport < MCHIP_CAP(SYS_CAP_SPEC_MAX_PORT_NUM); lport++)
    {
        dmps_port_info.gport = SYS_MAP_DRV_LPORT_TO_CTC_GPORT(gchip, lport);
        ret = sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, &port_type);
        if (ret < 0)
        {
            continue;
        }
        if ((port_type != SYS_DMPS_NETWORK_PORT)&&(port_type != SYS_DMPS_CPUMAC_NETWORK_PORT))
        {
            continue;
        }
        phy_info->lport[count++] = lport;
    }
    phy_info->count = count;
    return CTC_E_NONE;
}
STATIC int32
_sys_usw_global_wait_all_queues_to_empty(uint8 lchip)
{
    int32  ret = 0;
    sys_qos_shape_profile_t* shp_profile = NULL;
    uint32 depth;
    uint16 index;
    uint16  loop;
    uint32 gport;
    uint8  gchip;
    uint32  chan_id;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));
    shp_profile = mem_malloc(MEM_SYSTEM_MODULE, sizeof(sys_qos_shape_profile_t)*MCHIP_CAP(SYS_CAP_SPEC_MAX_PHY_PORT_NUM));
    if(shp_profile == NULL)
    {
        return CTC_E_NO_MEMORY;
    }
    sal_memset(shp_profile, 0, sizeof(sys_qos_shape_profile_t)*MCHIP_CAP(SYS_CAP_SPEC_MAX_PHY_PORT_NUM));
    for(loop=0; loop < MCHIP_CAP(SYS_CAP_SPEC_MAX_PHY_PORT_NUM); loop++)
    {
        gport = CTC_MAP_LPORT_TO_GPORT(gchip, loop);
        dmps_port_info.gport = gport;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
        if (SYS_COMMON_USELESS_CHANNEL == chan_id)
        {
            continue;
        }
        if (!DRV_FROM_TMM(lchip))
        {
            CTC_ERROR_GOTO(sys_usw_queue_get_profile_from_hw(lchip, gport, shp_profile + loop), ret, end_0);
        }
        CTC_ERROR_GOTO(sys_usw_queue_set_port_drop_en(lchip, gport, 1, shp_profile+loop), ret, end_0);
    }

    for(loop=0; loop < MCHIP_CAP(SYS_CAP_SPEC_MAX_PHY_PORT_NUM); loop++)
    {
        gport = CTC_MAP_LPORT_TO_GPORT(gchip, loop);
        dmps_port_info.gport = gport;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
        if (SYS_COMMON_USELESS_CHANNEL == chan_id)
        {
            continue;
        }
        index = 0;
        CTC_ERROR_GOTO(sys_usw_queue_get_port_depth(lchip, gport, &depth), ret, end_0);
        while (depth)
        {
            if ((index++) > 100)
            {
                ret = CTC_E_HW_TIME_OUT;
				goto end_0;
            }
            CTC_ERROR_GOTO(sys_usw_queue_get_port_depth(lchip, gport, &depth), ret, end_0);
        }
    }
end_0:
    for(loop=0; loop < MCHIP_CAP(SYS_CAP_SPEC_MAX_PHY_PORT_NUM); loop++)
    {
        gport = CTC_MAP_LPORT_TO_GPORT(gchip, loop);
        dmps_port_info.gport = gport;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
        if (SYS_COMMON_USELESS_CHANNEL == chan_id)
        {
            continue;
        }
        sys_usw_queue_set_port_drop_en(lchip, gport, 0, shp_profile+loop);
    }
    if(shp_profile)
    {
        mem_free(shp_profile);
    }
    return ret;
}
STATIC int32
_sys_usw_global_net_rx_enable(uint8 lchip, uint32 enable)
{
    uint32 field_val = enable?1:0;
    uint8  loop;
    uint8  loop1;
    uint32 base_table = 0;
    uint32 cmd = 0;

    if(!DRV_IS_TSINGMA(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }

    for(loop1=0; loop1 < 4; loop1++)
    {
        switch(loop1)
        {
            case 0:
               base_table = Sgmac0RxCfg0_t;
               break;
            case 1:
               base_table = Sgmac1RxCfg0_t;
               break;
            case 2:
               base_table = Sgmac2RxCfg0_t;
               break;
            default:
               base_table = Sgmac3RxCfg0_t;
               break;
        }
        for(loop=0; loop < 18; loop++)
        {
            cmd = DRV_IOW(base_table+loop, Sgmac0RxCfg0_cfgSgmac0RxPktEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
    }

    if(!enable)
    {
        CTC_ERROR_RETURN(_sys_usw_global_wait_all_queues_to_empty(lchip));
    }
    return CTC_E_NONE;
}
STATIC int32
_sys_usw_global_lb_hash_set_property(uint8 lchip, void* value)
{
    ctc_lb_hash_global_property_t* p_cfg = (ctc_lb_hash_global_property_t*)value;
    uint32 field_val = 0;
    uint32 cmd = 0;
    IpeHashMergeCtl_m merge_ctl;
    LagEngineCtl_m lag_ctl;
    sal_memset(&merge_ctl, 0, sizeof(IpeHashMergeCtl_m));
    CTC_PTR_VALID_CHECK(p_cfg);
    SYS_USW_LB_HASH_CHK_OFFSET(p_cfg->linkagg_lsh_hash_offset);
    SYS_USW_LB_HASH_CHK_OFFSET(p_cfg->linkagg_spm_hash_offset);
    SYS_USW_LB_HASH_CHK_OFFSET(p_cfg->stacking_lsh_hash_offset);
    cmd = DRV_IOR(LagEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lag_ctl));
    if(1 == GetLagEngineCtl(V, fabricMode_f, &lag_ctl))
    {
        SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "stacking use src_port_mode 3, not support config lb hash\n");
        return CTC_E_NOT_SUPPORT;
    }

    /*LINKAGG_LSH_HASH_OFFSET*/
    SetLagEngineCtl(V, portLagLshHashSelectCfg_f, &lag_ctl, (p_cfg->linkagg_lsh_hash_offset / 16));
    SetLagEngineCtl(V, portLagLshHashOffsetCfg_f, &lag_ctl, (p_cfg->linkagg_lsh_hash_offset % 16));

    /*LINKAGG_SPM_HASH_OFFSET*/
    SetLagEngineCtl(V, antFlowHashSelectCfg_f, &lag_ctl, (p_cfg->linkagg_spm_hash_offset / 16));
    SetLagEngineCtl(V, antFlowHashOffsetCfg_f, &lag_ctl, (p_cfg->linkagg_spm_hash_offset % 16));

    /*STACKING_TRUNK_LSH_HASH_OFFSET*/
    SetLagEngineCtl(V, cflexLagLshHashSelectCfg_f, &lag_ctl, (p_cfg->stacking_lsh_hash_offset/ 16));
    SetLagEngineCtl(V, cflexLagLshHashOffsetCfg_f, &lag_ctl, (p_cfg->stacking_lsh_hash_offset % 16));

    /*
    STACKING_PORT_HASH_EN
    mode 0: use profile or group cfg to select hash
    mode 1: use port lbn hash
    mode 2: local: use global cfg to select hash; fabric: re-calculate hash by header_hash and other info
    */
    field_val = (p_cfg->stacking_port_hash_en && DRV_FROM_TMM(lchip))?3:1;
    SetLagEngineCtl(V, sgHashMode_f, &lag_ctl, field_val);

    if (1 == p_cfg->stacking_port_hash_en)
    {
        field_val = 1;
        cmd = DRV_IOW(IpeFwdCflexUplinkLagHashCtl_t, IpeFwdCflexUplinkLagHashCtl_cflexHashType_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        field_val = 1;
        cmd = DRV_IOW(IpeFwdCflexUplinkLagHashCtl_t, IpeFwdCflexUplinkLagHashCtl_cflexHashTypeFabric_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        cmd = DRV_IOW(MetFifoCtl_t, MetFifoCtl_nonUcastToCflexLagHashMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    }
    else if (0 == p_cfg->stacking_port_hash_en || 2 == p_cfg->stacking_port_hash_en)
    {
        field_val = 0;
        cmd = DRV_IOW(IpeFwdCflexUplinkLagHashCtl_t, IpeFwdCflexUplinkLagHashCtl_cflexHashType_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        field_val = 2;
        cmd = DRV_IOW(IpeFwdCflexUplinkLagHashCtl_t, IpeFwdCflexUplinkLagHashCtl_cflexHashTypeFabric_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        field_val = 0;
        cmd = DRV_IOW(MetFifoCtl_t, MetFifoCtl_nonUcastToCflexLagHashMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    }

    cmd = DRV_IOW(LagEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lag_ctl));
    return CTC_E_NONE;
}
STATIC int32
_sys_usw_global_lb_hash_get_property(uint8 lchip, void* value)
{
    ctc_lb_hash_global_property_t* p_cfg = (ctc_lb_hash_global_property_t*)value;
    uint32 field_val = 0;
    uint32 field_Val1 = 0;
    uint32 cmd = 0;
    IpeHashMergeCtl_m merge_ctl;
    LagEngineCtl_m lagctl;
    sal_memset(&merge_ctl, 0, sizeof(IpeHashMergeCtl_m));
    CTC_PTR_VALID_CHECK(p_cfg);

    cmd = DRV_IOR(LagEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lagctl));
    /*LINKAGG_LSH_HASH_OFFSET*/
     p_cfg->linkagg_lsh_hash_offset = GetLagEngineCtl(V, portLagLshHashSelectCfg_f, &lagctl) << 4;
     p_cfg->linkagg_lsh_hash_offset += GetLagEngineCtl(V, portLagLshHashOffsetCfg_f, &lagctl);

    /*LINKAGG_SPM_HASH_OFFSET*/
     p_cfg->linkagg_spm_hash_offset = GetLagEngineCtl(V, antFlowHashSelectCfg_f, &lagctl) << 4;
     p_cfg->linkagg_spm_hash_offset  += GetLagEngineCtl(V, antFlowHashOffsetCfg_f, &lagctl);

    /*STACKING_TRUNK_LSH_HASH_OFFSET*/
     p_cfg->stacking_lsh_hash_offset = GetLagEngineCtl(V, cflexLagLshHashSelectCfg_f, &lagctl) << 4;
     p_cfg->stacking_lsh_hash_offset += GetLagEngineCtl(V, cflexLagLshHashOffsetCfg_f, &lagctl);

    /*STACKING_PORT_HASH_EN*/
    cmd = DRV_IOR(IpeFwdCflexUplinkLagHashCtl_t, IpeFwdCflexUplinkLagHashCtl_cflexHashType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    cmd = DRV_IOR(LagEngineCtl_t, LagEngineCtl_sgHashMode_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_Val1));
    field_val = (1 == field_Val1) ? 0 : (1 == field_val ? 1 : 2);
    p_cfg->stacking_port_hash_en = field_val;

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_global_set_eslb_en(uint8 lchip)
{
    uint16 lport = 0;
    int32 ret = 0;
    uint8 gchip = 0;
    uint32 gport = 0;

    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));
    for (lport = 0; lport < MCHIP_CAP(SYS_CAP_SPEC_MAX_PORT_NUM); lport++)
    {
        gport = SYS_MAP_DRV_LPORT_TO_CTC_GPORT(gchip, lport);
        ret = sys_usw_port_api_set_property(lchip, gport, CTC_PORT_PROP_ESLB, 0);
        ret = ret?ret:sys_usw_port_api_set_property(lchip, gport, CTC_PORT_PROP_ESID, 0);
        if (ret < 0)
        {
            return ret;
        }
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_global_set_xpipe_action(uint8 lchip,             void* value)
{
    ds1_t ds = {0};
    ctc_register_xpipe_action_t* p_action = value;
    uint32 srcGuaranteeEn[3] = {0};
    uint32 index = 0;
    uint32 cmd = 0;
    uint8 step = 0;
    uint32 tbl_id = 0;

    if (!DRV_FROM_TM(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }
    CTC_MAX_VALUE_CHECK(p_action->priority, 15);
    CTC_MAX_VALUE_CHECK(p_action->color, MAX_CTC_QOS_COLOR-1);
    if (DRV_FROM_AT(lchip))
    {
        uint8 end = 0;
        CTC_MAX_VALUE_CHECK(p_action->is_high_pri, 2);
        /* unicast */
        cmd = DRV_IOR(UcQWriteGuaranteeCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        step = UcQWriteGuaranteeCtl_prio_1_sel_f - UcQWriteGuaranteeCtl_prio_0_sel_f;
        index = (p_action->color? p_action->color: 0);
        end = (p_action->color? p_action->color + 1: 4);
        for (; index < end; index++)
        {
            SetUcQWriteGuaranteeCtl(V, prio_0_sel_f + step * ((p_action->priority << 2) | index), ds, p_action->is_high_pri);
        }
        cmd = DRV_IOW(UcQWriteGuaranteeCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    }
    /* muticast */
    tbl_id = (DRV_FROM_AT(lchip))? McQWriteGuaranteeCtl_t: QWriteGuaranteeCtl_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    if (DRV_IS_TSINGMA(lchip))
    {
        if ((!GetQWriteGuaranteeCtl(V, glbGuaranteeEn_f, ds) || !GetQWriteGuaranteeCtl(V, mode_f, ds)))
        {
            return CTC_E_INVALID_PARAM;
        }

        GetQWriteGuaranteeCtl(A, srcGuaranteeEn_f, ds, srcGuaranteeEn);
    }
    else if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
    {
        GetQWriteGuaranteeCtl(A, prioGuaranteeEn_f, ds, srcGuaranteeEn);
    }
    else
    {
        GetMcQWriteGuaranteeCtl(A, prioGuaranteeEn_f, ds, srcGuaranteeEn);
    }
    if (p_action->color)
    {
        index = ((p_action->priority & 0xf) << 2) + p_action->color;
        if (p_action->is_high_pri)
        {
            CTC_BIT_UNSET(srcGuaranteeEn[index / BITS_NUM_OF_WORD], index % BITS_NUM_OF_WORD);
            if (DRV_FROM_TMM(lchip))
            {
                CTC_BIT_SET(srcGuaranteeEn[index / BITS_NUM_OF_WORD], index % BITS_NUM_OF_WORD);
            }
        }
        else
        {
            CTC_BIT_SET(srcGuaranteeEn[index / BITS_NUM_OF_WORD], index % BITS_NUM_OF_WORD);
            if (DRV_FROM_TMM(lchip))
            {
                CTC_BIT_UNSET(srcGuaranteeEn[index / BITS_NUM_OF_WORD], index % BITS_NUM_OF_WORD);
            }
        }
    }
    else
    {
        uint8 i = 0;
        for (i = 0; i < 4; i++)
        {
            index = ((p_action->priority & 0xf) << 2) + i;
            if (p_action->is_high_pri)
            {
                CTC_BIT_UNSET(srcGuaranteeEn[index / BITS_NUM_OF_WORD], index % BITS_NUM_OF_WORD);
                if (DRV_FROM_TMM(lchip))
                {
                    CTC_BIT_SET(srcGuaranteeEn[index / BITS_NUM_OF_WORD], index % BITS_NUM_OF_WORD);
                }
            }
            else
            {
                CTC_BIT_SET(srcGuaranteeEn[index / BITS_NUM_OF_WORD], index % BITS_NUM_OF_WORD);
                if (DRV_FROM_TMM(lchip))
                {
                    CTC_BIT_UNSET(srcGuaranteeEn[index / BITS_NUM_OF_WORD], index % BITS_NUM_OF_WORD);
                }
            }
        }
    }
    if (DRV_IS_TSINGMA(lchip))
    {
        SetQWriteGuaranteeCtl(A, srcGuaranteeEn_f, ds, srcGuaranteeEn);
    }
    else if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
    {
        SetQWriteGuaranteeCtl(A, prioGuaranteeEn_f, ds, srcGuaranteeEn);
    }
    else
    {
        SetMcQWriteGuaranteeCtl(A, prioGuaranteeEn_f, ds, srcGuaranteeEn);
    }
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, 0, cmd, ds);
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_global_get_xpipe_action(uint8 lchip,             void* value)
{
    ctc_register_xpipe_action_t *p_action = value;
    uint32 srcGuaranteeEn[3] = {0};
    uint32 index = 0;
    uint32 cmd = 0;
    ds1_t ds;
    uint8 step = 0;

    if (DRV_IS_DUET2(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }
    CTC_MAX_VALUE_CHECK(p_action->priority, 15);
    CTC_MAX_VALUE_CHECK(p_action->color, MAX_CTC_QOS_COLOR-1);
    if (DRV_FROM_AT(lchip))
    {
        /* unicast */
        cmd = DRV_IOR(UcQWriteGuaranteeCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        step = UcQWriteGuaranteeCtl_prio_1_sel_f - UcQWriteGuaranteeCtl_prio_0_sel_f;
        p_action->is_high_pri = GetUcQWriteGuaranteeCtl(V, prio_0_sel_f + step * ((p_action->priority << 2) | p_action->color), ds);
        return CTC_E_NONE;
    }
    cmd = DRV_IOR(QWriteGuaranteeCtl_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, 0, cmd, ds);
    if (DRV_IS_TSINGMA(lchip))
    {
        GetQWriteGuaranteeCtl(A, srcGuaranteeEn_f, ds, srcGuaranteeEn);
    }
    else
    {
        GetQWriteGuaranteeCtl(A, prioGuaranteeEn_f, ds, srcGuaranteeEn);
    }
    index = ((p_action->priority&0xf) << 2) + p_action->color;
    if (CTC_IS_BIT_SET(srcGuaranteeEn[index / BITS_NUM_OF_WORD], index % BITS_NUM_OF_WORD))
    {
        p_action->is_high_pri = ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))? 1 : 0;
    }
    else
    {
        if (DRV_IS_TSINGMA(lchip))
        {
            p_action->is_high_pri = (GetQWriteGuaranteeCtl(V, mode_f, ds) && GetQWriteGuaranteeCtl(V, glbGuaranteeEn_f, ds)) ? 1 : 0;
        }
        else
        {
            p_action->is_high_pri = ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))? 0 : 1;
        }
    }
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_global_set_xpipe_classify(uint8 lchip, void* value, uint8 pp_id, uint8 dp_id)
{
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint8  loop = 0;
    uint8  valid = 0;
    uint8  step = 0;
    uint8  index = DRV_FROM_AT(lchip) ? 0 : dp_id;
    hw_mac_addr_t mac_addr;
    hw_mac_addr_t mac_addr_mask;
    mac_addr_t usr_mac_addr;
    mac_addr_t usr_mac_addr_mask;
    NetRxPriorityChannelCam_m netrx_cam;
    NetRxPriorityChannelCamValid_m netrx_cam_valid;
    NetRxAdmissionCfg_m netrx_cfg;
    ctc_register_xpipe_classify_t* p_classify = value;
    ctc_field_key_t* field_tmp = NULL;
    CTC_MAX_VALUE_CHECK(p_classify->index, (DRV_IS_TMG(lchip) ? 7 : 3));
    CTC_PTR_VALID_CHECK(p_classify->field_list);

    sal_memset(mac_addr, 0, sizeof(mac_addr));
    sal_memset(mac_addr_mask, 0, sizeof(mac_addr_mask));
    sal_memset(&netrx_cam, 0, sizeof(netrx_cam));
    sal_memset(&netrx_cfg, 0, sizeof(netrx_cfg));

    lchip = SYS_PP_BASE(lchip) + pp_id;
    step = NetRxPriorityChannelCam_array_0_dot1pTagged_f - NetRxPriorityChannelCam_array_0_dot1pPcp_f;
    cmd = DRV_IOR(NetRxPriorityChannelCam_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_DP_EN(cmd, dp_id), &netrx_cam));
    for(loop = 0; loop < SYS_USW_XPIPE_CLASSIFY_FILED_MAX; loop++)
    {
        SetNetRxPriorityChannelCam(V, array_0_dot1pPcp_f     + p_classify->index + step*loop, &netrx_cam, 0);
        SetNetRxPriorityChannelCam(V, array_0_dot1pPcpMask_f + p_classify->index + step*loop, &netrx_cam, 0);
    }
    step = NetRxPriorityChannelCam_array_1_dot1pPcp_f - NetRxPriorityChannelCam_array_0_dot1pPcp_f;
    for(loop = 0; loop < p_classify->field_cnt && p_classify->valid; loop++)
    {
        field_tmp = p_classify->field_list + loop;
        switch(field_tmp->type)
        {
        case CTC_FIELD_KEY_MAC_DA:
            {
            CTC_MAX_VALUE_CHECK(p_classify->index, 0);
            CTC_PTR_VALID_CHECK(field_tmp->ext_data);
            CTC_PTR_VALID_CHECK(field_tmp->ext_mask);
            sal_memcpy(usr_mac_addr, field_tmp->ext_data, sizeof(mac_addr_t));
            sal_memcpy(usr_mac_addr_mask, field_tmp->ext_mask, sizeof(mac_addr_t));
            if ((usr_mac_addr_mask[0] == 0) && (usr_mac_addr_mask[1] == 0)
                && (usr_mac_addr_mask[2] == 0) && (usr_mac_addr_mask[3] == 0)
                && (usr_mac_addr_mask[4] == 0) && (usr_mac_addr_mask[5] == 0))
            {
                sal_memset(usr_mac_addr_mask, 0xFF, sizeof(mac_addr_t));
            }
            SYS_USW_SET_HW_MAC(mac_addr, usr_mac_addr);
            SYS_USW_SET_HW_MAC(mac_addr_mask, usr_mac_addr_mask);
            cmd = DRV_IOR(NetRxAdmissionCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_DP_EN(cmd, dp_id), &netrx_cfg));
            SetNetRxAdmissionCfg(V, routerMacDaValueLow_f, &netrx_cfg, mac_addr[0]);
            SetNetRxAdmissionCfg(V, routerMacDaValueHigh_f, &netrx_cfg,  mac_addr[1]);
            SetNetRxAdmissionCfg(V, routerMacDaMaskLow_f, &netrx_cfg, mac_addr_mask[0]);
            SetNetRxAdmissionCfg(V, routerMacDaMaskHigh_f, &netrx_cfg, mac_addr_mask[1]);
            SetNetRxAdmissionCfg(V, routerMacChkEn_f, &netrx_cfg,(mac_addr[0] || mac_addr[1]) ? 1 : 0);
            cmd = DRV_IOW(NetRxAdmissionCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_DP_EN(cmd, dp_id), &netrx_cfg));
            CTC_BIT_SET(valid, 0);
            }
            break;
        case CTC_FIELD_KEY_MACDA_HIT:
            CTC_BIT_SET(valid, 1);
            SetNetRxPriorityChannelCam(V, array_0_routerMacValid_f + p_classify->index*step, &netrx_cam, field_tmp->data);
            SetNetRxPriorityChannelCam(V, array_0_routerMacValidMask_f + p_classify->index*step, &netrx_cam, field_tmp->mask);
            break;
        case CTC_FIELD_KEY_PKT_STAG_VALID:
            CTC_BIT_SET(valid, 1);
            SetNetRxPriorityChannelCam(V, array_0_dot1pTagged_f + p_classify->index*step, &netrx_cam, field_tmp->data);
            SetNetRxPriorityChannelCam(V, array_0_dot1pTaggedMask_f + p_classify->index*step, &netrx_cam, field_tmp->mask);
            break;
        case CTC_FIELD_KEY_SVLAN_ID:
            CTC_BIT_SET(valid, 1);
            SetNetRxPriorityChannelCam(V, array_0_dot1pVlanId_f + p_classify->index*step, &netrx_cam, field_tmp->data);
            SetNetRxPriorityChannelCam(V, array_0_dot1pVlanIdMask_f + p_classify->index*step, &netrx_cam, field_tmp->mask);
            break;
        case CTC_FIELD_KEY_STAG_COS:
            CTC_BIT_SET(valid, 1);
            SetNetRxPriorityChannelCam(V, array_0_dot1pPcp_f + p_classify->index*step, &netrx_cam, field_tmp->data);
            SetNetRxPriorityChannelCam(V, array_0_dot1pPcpMask_f + p_classify->index*step, &netrx_cam,  field_tmp->mask);
            break;
        case CTC_FIELD_KEY_ETHER_TYPE:
            CTC_BIT_SET(valid, 1);
            SetNetRxPriorityChannelCam(V, array_0_tpid_f + p_classify->index*step, &netrx_cam, field_tmp->data);
            SetNetRxPriorityChannelCam(V, array_0_tpidMask_f + p_classify->index*step, &netrx_cam, field_tmp->mask);
            break;
        case CTC_FIELD_KEY_IS_IP_PKT:
            CTC_BIT_SET(valid, 1);
            SetNetRxPriorityChannelCam(V, array_0_ipUcValid_f + p_classify->index*step, &netrx_cam, field_tmp->data);
            SetNetRxPriorityChannelCam(V, array_0_ipUcValidMask_f + p_classify->index*step, &netrx_cam, field_tmp->mask);
            break;
        case CTC_FIELD_KEY_IP_DSCP:
            CTC_BIT_SET(valid, 1);
            SetNetRxPriorityChannelCam(V, array_0_ipDscp_f + p_classify->index*step, &netrx_cam, field_tmp->data);
            SetNetRxPriorityChannelCam(V, array_0_ipDscpMask_f + p_classify->index*step, &netrx_cam, field_tmp->mask);
            break;
        case CTC_FIELD_KEY_IP_PROTOCOL:
            CTC_BIT_SET(valid, 1);
            SetNetRxPriorityChannelCam(V, array_0_ipProtocol_f + p_classify->index*step, &netrx_cam, field_tmp->data);
            SetNetRxPriorityChannelCam(V, array_0_ipProtocolMask_f + p_classify->index*step, &netrx_cam, field_tmp->mask);
            break;
        case CTC_FIELD_KEY_UDF:
            CTC_BIT_SET(valid, 1);
            SetNetRxPriorityChannelCam(V, array_0_l4Data_f + p_classify->index*step, &netrx_cam, field_tmp->data);
            SetNetRxPriorityChannelCam(V, array_0_l4DataMask_f + p_classify->index*step, &netrx_cam, field_tmp->mask);
            break;
        case CTC_FIELD_KEY_PORT:
            field_val = p_classify->obm_priority;
            cmd = DRV_IOW(NetRxReserved_t, NetRxReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, DRV_CMD_DP_EN(cmd, dp_id), &field_val));
            break;
        default:
            return CTC_E_INTR_INVALID_PARAM;
        }
    }
    cmd = DRV_IOW(NetRxPriorityChannelCam_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_DP_EN(cmd, dp_id), &netrx_cam));

    cmd = DRV_IOR(NetRxPriorityChannelCamValid_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_DP_EN(cmd, dp_id), &netrx_cam_valid));
    field_val = GetNetRxPriorityChannelCamValid(V, valid_f, &netrx_cam_valid);
    CTC_IS_BIT_SET(valid, 1) ? CTC_BIT_SET(field_val, p_classify->index) : CTC_BIT_UNSET(field_val, p_classify->index);
    SetNetRxPriorityChannelCamValid(V, valid_f, &netrx_cam_valid, field_val);
    cmd = DRV_IOW(NetRxPriorityChannelCamValid_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_DP_EN(cmd, dp_id), &netrx_cam_valid));

    if(p_classify->index == 0 && (p_classify->valid == 0 || !CTC_IS_BIT_SET(valid, 0)))
    {
        cmd = DRV_IOR(NetRxAdmissionCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_DP_EN(cmd, dp_id), &netrx_cfg));
        SetNetRxAdmissionCfg(V, routerMacDaValueLow_f, &netrx_cfg, 0);
        SetNetRxAdmissionCfg(V, routerMacDaValueHigh_f, &netrx_cfg,  0);
        SetNetRxAdmissionCfg(V, routerMacDaMaskLow_f, &netrx_cfg, 0);
        SetNetRxAdmissionCfg(V, routerMacDaMaskHigh_f, &netrx_cfg, 0);
        SetNetRxAdmissionCfg(V, routerMacChkEn_f, &netrx_cfg,0);
        cmd = DRV_IOW(NetRxAdmissionCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_DP_EN(cmd, dp_id), &netrx_cfg));
    }
    return  CTC_E_NONE;
}

STATIC int32
_sys_usw_global_get_xpipe_classify(uint8 lchip, void* value, uint8 pp_id, uint8 dp_id)
{
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint8  loop = 0;
    uint8  enable = 0;
    uint8  step = 0;
    uint8  index = DRV_FROM_AT(lchip) ? 0 : dp_id;
    hw_mac_addr_t mac_addr;
    hw_mac_addr_t mac_addr_mask;
    mac_addr_t usr_mac_addr;
    mac_addr_t usr_mac_addr_mask;
    NetRxPriorityChannelCam_m netrx_cam;
    NetRxPriorityChannelCamValid_m netrx_cam_valid;
    NetRxAdmissionCfg_m netrx_cfg;
    ctc_register_xpipe_classify_t* p_classify = (ctc_register_xpipe_classify_t*)value;
    ctc_field_key_t* field_tmp = NULL;
    CTC_MAX_VALUE_CHECK(p_classify->index, (DRV_IS_TMG(lchip) ? 7 : 3));
    CTC_PTR_VALID_CHECK(p_classify->field_list);

    sal_memset(mac_addr, 0, sizeof(mac_addr));
    sal_memset(mac_addr_mask, 0, sizeof(mac_addr_mask));

    lchip = SYS_PP_BASE(lchip) + pp_id;
    cmd = DRV_IOR(NetRxPriorityChannelCamValid_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_DP_EN(cmd, dp_id), &netrx_cam_valid));
    field_val = GetNetRxPriorityChannelCamValid(V, valid_f, &netrx_cam_valid);
    p_classify->valid = CTC_IS_BIT_SET(field_val, p_classify->index);

    step = NetRxPriorityChannelCam_array_1_dot1pPcpMask_f - NetRxPriorityChannelCam_array_0_dot1pPcpMask_f;
    cmd = DRV_IOR(NetRxPriorityChannelCam_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, DRV_CMD_DP_EN(cmd, dp_id), &netrx_cam));
    for(loop = 0; loop < p_classify->field_cnt; loop++)
    {
        field_tmp = p_classify->field_list + loop;
        if(!p_classify->valid  && field_tmp->type != CTC_FIELD_KEY_MAC_DA)
        {
            continue;
        }
        switch(field_tmp->type)
        {
        case CTC_FIELD_KEY_MAC_DA:
            {
            cmd = DRV_IOR(NetRxAdmissionCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &netrx_cfg));
            mac_addr[0] = GetNetRxAdmissionCfg(V, routerMacDaValueLow_f, &netrx_cfg);
            mac_addr[1] = GetNetRxAdmissionCfg(V, routerMacDaValueHigh_f, &netrx_cfg);
            mac_addr_mask[0] = GetNetRxAdmissionCfg(V, routerMacDaMaskLow_f, &netrx_cfg);
            mac_addr_mask[1] = GetNetRxAdmissionCfg(V, routerMacDaMaskHigh_f, &netrx_cfg);
            enable = GetNetRxAdmissionCfg(V, routerMacChkEn_f, &netrx_cfg);
            if(enable && field_tmp->ext_data && field_tmp->ext_data && p_classify->index == 0)
            {
                SYS_USW_SET_USER_MAC(usr_mac_addr, mac_addr);
                SYS_USW_SET_USER_MAC(usr_mac_addr_mask, mac_addr_mask);
                sal_memcpy(field_tmp->ext_data, usr_mac_addr, sizeof(mac_addr_t));
                sal_memcpy(field_tmp->ext_mask, usr_mac_addr_mask, sizeof(mac_addr_t));
            }
            }
            break;
        case CTC_FIELD_KEY_MACDA_HIT:
            field_tmp->data = GetNetRxPriorityChannelCam(V, array_0_routerMacValid_f + p_classify->index*step, &netrx_cam);
            field_tmp->mask = GetNetRxPriorityChannelCam(V, array_0_routerMacValidMask_f + p_classify->index*step, &netrx_cam);
            break;
        case CTC_FIELD_KEY_PKT_STAG_VALID:
            field_tmp->data = GetNetRxPriorityChannelCam(V, array_0_dot1pTagged_f + p_classify->index*step, &netrx_cam);
            field_tmp->mask = GetNetRxPriorityChannelCam(V, array_0_dot1pTaggedMask_f + p_classify->index*step, &netrx_cam);
            break;
        case CTC_FIELD_KEY_SVLAN_ID:
            field_tmp->data = GetNetRxPriorityChannelCam(V, array_0_dot1pVlanId_f + p_classify->index*step, &netrx_cam);
            field_tmp->mask = GetNetRxPriorityChannelCam(V, array_0_dot1pVlanIdMask_f + p_classify->index*step, &netrx_cam);
            break;
        case CTC_FIELD_KEY_STAG_COS:
            field_tmp->data = GetNetRxPriorityChannelCam(V, array_0_dot1pPcp_f + p_classify->index*step, &netrx_cam);
            field_tmp->mask = GetNetRxPriorityChannelCam(V, array_0_dot1pPcpMask_f + p_classify->index*step, &netrx_cam);
            break;
        case CTC_FIELD_KEY_ETHER_TYPE:
            field_tmp->data = GetNetRxPriorityChannelCam(V, array_0_tpid_f + p_classify->index*step, &netrx_cam);
            field_tmp->mask = GetNetRxPriorityChannelCam(V, array_0_tpidMask_f + p_classify->index*step, &netrx_cam);
            break;
        case CTC_FIELD_KEY_IS_IP_PKT:
            field_tmp->data = GetNetRxPriorityChannelCam(V, array_0_ipUcValid_f + p_classify->index*step, &netrx_cam);
            field_tmp->mask = GetNetRxPriorityChannelCam(V, array_0_ipUcValidMask_f + p_classify->index*step, &netrx_cam);
            break;
        case CTC_FIELD_KEY_IP_DSCP:
            field_tmp->data = GetNetRxPriorityChannelCam(V, array_0_ipDscp_f + p_classify->index*step, &netrx_cam);
            field_tmp->mask = GetNetRxPriorityChannelCam(V, array_0_ipDscpMask_f + p_classify->index*step, &netrx_cam);
            break;
        case CTC_FIELD_KEY_IP_PROTOCOL:
            field_tmp->data = GetNetRxPriorityChannelCam(V, array_0_ipProtocol_f + p_classify->index*step, &netrx_cam);
            field_tmp->mask = GetNetRxPriorityChannelCam(V, array_0_ipProtocolMask_f + p_classify->index*step, &netrx_cam);
            break;
        case CTC_FIELD_KEY_UDF:
            field_tmp->data = GetNetRxPriorityChannelCam(V, array_0_l4Data_f + p_classify->index*step, &netrx_cam);
            field_tmp->mask = GetNetRxPriorityChannelCam(V, array_0_l4DataMask_f + p_classify->index*step, &netrx_cam);
            break;
        case CTC_FIELD_KEY_PORT:
            cmd = DRV_IOR(NetRxReserved_t, NetRxReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, DRV_CMD_DP_EN(cmd, dp_id), &field_val));
            p_classify->obm_priority = field_val;
            break;
        default:
            break;
        }
    }

    return  CTC_E_NONE;
}

STATIC int32
_sys_usw_global_xpipe_classify_get_dp_en(uint8 lchip, ctc_register_xpipe_classify_t* p_classify, uint8* dp_en, uint32* pp_id, uint32* dp_id)
{
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    ctc_field_key_t* field_tmp = NULL;
    uint32 chan_id = 0;
    uint8  loop  = 0;

    CTC_PTR_VALID_CHECK(p_classify->field_list);
    if (!DRV_FROM_TMM(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }
    for(loop = 0; loop < p_classify->field_cnt; loop++)
    {
        field_tmp = p_classify->field_list + loop;
        if (CTC_FIELD_KEY_PORT == field_tmp->type)
        {
            if(!SYS_GPORT_IS_NETWORK_PORT(field_tmp->data))
            {
                return CTC_E_INVALID_GLOBAL_PORT;
            }
            *dp_en = 1;
            dmps_port_info.gport = field_tmp->data;
            if (DRV_FROM_AT(lchip))
            {
                CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PP_ID, pp_id));
                CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_DP_ID, dp_id));
            }
            else
            {
                CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
                *dp_id = chan_id/MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM);
            }
        }
    }
    return CTC_E_NONE;
}

STATIC int32
sys_usw_global_set_xpipe_classify(uint8 lchip, void* value)
{
    ctc_register_xpipe_classify_t* p_classify = value;
    uint32 pp_id = 0;
    uint32 dp_id = 0;
    uint8  dp_en = 0;
    uint8  loop  = 0;

    CTC_ERROR_RETURN(_sys_usw_global_xpipe_classify_get_dp_en(lchip, p_classify, &dp_en, &pp_id, &dp_id));
    if (dp_en)
    {
        CTC_MAX_VALUE_CHECK(p_classify->obm_priority, MCHIP_CAP(SYS_CAP_QOS_CLASS_OBM_PRIORITY_MAX) - 1);
        CTC_ERROR_RETURN(_sys_usw_global_set_xpipe_classify(lchip, value, pp_id, dp_id));
    }
    else
    {
        for(loop = 0; loop < SYS_PP_NUM(lchip) * MCHIP_CAP(SYS_CAP_DP_MAX_NUM); loop++)
        {
            CTC_ERROR_RETURN(_sys_usw_global_set_xpipe_classify(lchip, value, loop/MCHIP_CAP(SYS_CAP_DP_MAX_NUM), loop%MCHIP_CAP(SYS_CAP_DP_MAX_NUM)));
        }
    }
    return CTC_E_NONE;
}

STATIC int32
sys_usw_global_get_xpipe_classify(uint8 lchip, void* value)
{
    ctc_register_xpipe_classify_t* p_classify = value;
    uint32 pp_id = 0;
    uint32 dp_id = 0;
    uint8  dp_en = 0;

    CTC_ERROR_RETURN(_sys_usw_global_xpipe_classify_get_dp_en(lchip, p_classify, &dp_en, &pp_id, &dp_id));
    if (dp_en)
    {
        CTC_ERROR_RETURN(_sys_usw_global_get_xpipe_classify(lchip, value, pp_id, dp_id));
    }
    else
    {
        CTC_ERROR_RETURN(_sys_usw_global_get_xpipe_classify(lchip, value, 0, 0));
    }
    return CTC_E_NONE;
}

int32
_sys_usw_global_get_martian_address(uint8 lchip, ctc_global_martian_addr_t* p_martian_addr)
{
    ds_t ds = {0};
    uint32 cmd = 0;
    if (!DRV_FROM_TMM(lchip) && CTC_IP_VER_6 == p_martian_addr->ip_ver)
    {
        return CTC_E_NOT_SUPPORT;
    }
    if (CTC_IP_VER_4 == p_martian_addr->ip_ver)
    {
        uint32 mask = 0;
        cmd = DRV_IOR(IpeRouteMartianAddr_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        if (0 == p_martian_addr->index)
        {
            GetIpeRouteMartianAddr(A, flex0Value_f, ds, &p_martian_addr->addr.ipv4);
            GetIpeRouteMartianAddr(A, flex0Mask_f, ds, &mask);
            IPV4_MASK_TO_LEN(mask, p_martian_addr->masklen);
        }
        else
        {
            GetIpeRouteMartianAddr(A, flex1Value_f, ds, &p_martian_addr->addr.ipv4);
            GetIpeRouteMartianAddr(A, flex1Mask_f, ds, &mask);
            IPV4_MASK_TO_LEN(mask, p_martian_addr->masklen);
        }
    }
    else
    {
        ipv6_addr_t ipv6_addr_mask;
        cmd = DRV_IOR(IpeLookupRouteCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        GetIpeLookupRouteCtl(A, martianAddr_f, ds, p_martian_addr->addr.ipv6);
        SYS_IPV6_ADDRESS_SORT(p_martian_addr->addr.ipv6);
        GetIpeLookupRouteCtl(A, martianAddrMask_f, ds, ipv6_addr_mask);
        SYS_IPV6_ADDRESS_SORT(ipv6_addr_mask);
        IPV6_MASK_TO_LEN(ipv6_addr_mask, p_martian_addr->masklen);
    }
    return CTC_E_NONE;
}

int32
_sys_usw_global_set_martian_address(uint8 lchip, ctc_global_martian_addr_t* p_martian_addr)
{
    ds_t ds = {0};
    ds_t ipe_lookup_route_ctl = {0};
    uint32 cmd = 0;
    uint32 check_en = 0;

    if (!DRV_FROM_TMM(lchip) && CTC_IP_VER_6 == p_martian_addr->ip_ver)
    {
        return CTC_E_NOT_SUPPORT;
    }
    CTC_MAX_VALUE_CHECK(p_martian_addr->masklen, p_martian_addr->ip_ver?128:32);
    cmd = DRV_IOR(IpeLookupRouteCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_lookup_route_ctl));
    GetIpeLookupRouteCtl(A, martianCheckEn_f, ipe_lookup_route_ctl, &check_en);
    if (CTC_IP_VER_4 == p_martian_addr->ip_ver)
    {
        uint32 mask = 0;
        cmd = DRV_IOR(IpeRouteMartianAddr_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

        if (0 == p_martian_addr->index)
        {
            IPV4_LEN_TO_MASK(mask, p_martian_addr->masklen);
            SetIpeRouteMartianAddr(A, flex0Value_f, ds, &p_martian_addr->addr.ipv4);
            SetIpeRouteMartianAddr(A, flex0Mask_f, ds, &mask);
            p_martian_addr->masklen ? (check_en |= 0x10) : (check_en &= 0xffffffef);
        }
        else
        {
            IPV4_LEN_TO_MASK(mask, p_martian_addr->masklen);
            SetIpeRouteMartianAddr(A, flex1Value_f, ds, &p_martian_addr->addr.ipv4);
            SetIpeRouteMartianAddr(A, flex1Mask_f, ds, &mask);
            p_martian_addr->masklen ? (check_en |= 0x20) : (check_en &= 0xffffffdf);
        }
        SetIpeLookupRouteCtl(V, martianCheckEn_f, ipe_lookup_route_ctl, check_en);
        cmd = DRV_IOW(IpeLookupRouteCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_lookup_route_ctl));
        cmd = DRV_IOW(IpeRouteMartianAddr_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    }
    else
    {
        ipv6_addr_t ipv6_addr;
        cmd = DRV_IOR(IpeLookupRouteCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        /* adjust endian */
        ipv6_addr[0] = sal_htonl(p_martian_addr->addr.ipv6[0]);
        ipv6_addr[1] = sal_htonl(p_martian_addr->addr.ipv6[1]);
        ipv6_addr[2] = sal_htonl(p_martian_addr->addr.ipv6[2]);
        ipv6_addr[3] = sal_htonl(p_martian_addr->addr.ipv6[3]);
        SYS_IPV6_ADDRESS_SORT(ipv6_addr);
        SetIpeLookupRouteCtl(A, martianAddr_f, ds, ipv6_addr);
        IPV6_LEN_TO_MASK(ipv6_addr, p_martian_addr->masklen);
        SetIpeLookupRouteCtl(A, martianAddrMask_f, ds, ipv6_addr);
        p_martian_addr->masklen ? (check_en |= 0x40000) : (check_en &= 0xfffbffff);
        SetIpeLookupRouteCtl(V, martianCheckEn_f, ds, check_en);
        cmd = DRV_IOW(IpeLookupRouteCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    }
    return CTC_E_NONE;
}

int32
_sys_usw_global_set_eco_hibernate_en(uint8 lchip, uint32 enable)
{
    ds_t ds_zero = {0};
    ds_t ds_set = {0};
    uint32 cmd = 0;
    uint32 idx = 0;
    uint16 num = 0;
    uint8 is_fld = 0;
    uint32* p_value = NULL;
    sys_usw_register_eco_tbl_t hibernate_tab[] =
    {
        {CtcMiscCtlClkEn_t, DRV_ENTRY_FLAG, 1, 0},
        {CpuMacCtlEnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {CtcHsCtlEnClk_t, DRV_ENTRY_FLAG, 4, 0},
        {CtcCsCtlEnClk_t, DRV_ENTRY_FLAG, 4, 0},
        {CtcFlexeCrossCtlEnClk_t, DRV_ENTRY_FLAG, 2, 0},
        {CtcFlexeShimCtlEnClk_t, DRV_ENTRY_FLAG, 2, 0},
        {CtcDpTxCtlClockEn_t, DRV_ENTRY_FLAG, 2, 0},
        {CtcDpRxCtlClockEn_t, DRV_ENTRY_FLAG, 2, 0},
        {CpuMacCtlEnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {CtcIpeTxClkEn_t, DRV_ENTRY_FLAG, 1, 0},
        {SupEnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {SupEnClkCtl_t, DRV_ENTRY_FLAG, 1, 0},
        {ProgramAclTcamLowPowerCtl_t, DRV_ENTRY_FLAG, 1, 0},
        {Dp0Mac0HssIddqEnable_t, DRV_ENTRY_FLAG, 1, 1},
        {Dp0Mac1HssIddqEnable_t, DRV_ENTRY_FLAG, 1, 1},
        {Dp0Mac2HssIddqEnable_t, DRV_ENTRY_FLAG, 1, 1},
        {Dp0Mac3HssIddqEnable_t, DRV_ENTRY_FLAG, 1, 1},
        {Dp1Mac0HssIddqEnable_t, DRV_ENTRY_FLAG, 1, 1},
        {Dp1Mac1HssIddqEnable_t, DRV_ENTRY_FLAG, 1, 1},
        {Dp1Mac2HssIddqEnable_t, DRV_ENTRY_FLAG, 1, 1},
        {Dp1Mac3HssIddqEnable_t, DRV_ENTRY_FLAG, 1, 1},
        {CpuMacHssIddqEnable_t, DRV_ENTRY_FLAG, 1, 1},
    };
    
    /*TBD need add serdes */
    sys_usw_register_eco_tbl_t at_hibernate_tab[] =
    {
        {CtcMiscCtlModuleEn_t, DRV_ENTRY_FLAG, 1, 0},
        {CtcBufStoreProcTopCtlModuleEnable_t, DRV_ENTRY_FLAG, 1, 0},
        {CtcBufStoreSliceQuadCtlModuleEnable_t, DRV_ENTRY_FLAG, 1, 0},
        {CtcEpeTxModuleEnable_t, DRV_ENTRY_FLAG, 1, 0},
        {CtcPreBrCtlModuleEnable_t, DRV_ENTRY_FLAG, 1, 0},
        {CtcQMgrEnqModuleEnable_t, DRV_ENTRY_FLAG, 1, 0},
        {CpuMacCtlEnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {CtcMacCtlEnClk_t, DRV_ENTRY_FLAG, 20, 0},
        {EcpuDmaEnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {Ecpu00EnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {Ecpu01EnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {Ecpu10EnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {Ecpu11EnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {EcpuSupEnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {GpioEnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {McPcs800EnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {QspiEnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {SupEnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {UartEnClk_t, DRV_ENTRY_FLAG, 1, 0},
        {CtcIpeTxClkEn_t, DRV_ENTRY_FLAG, 1, 0},
        {McuMapRegClkEn_t, DRV_ENTRY_FLAG, 20, 0},
        {PGRlmSlice0ClkEnable_t, DRV_ENTRY_FLAG, 1, 0},
        {PGRlmSlice1ClkEnable_t, DRV_ENTRY_FLAG, 1, 0},
        {PGRlmSlice2ClkEnable_t, DRV_ENTRY_FLAG, 1, 0},
        {PGRlmSlice3ClkEnable_t, DRV_ENTRY_FLAG, 1, 0},
        {CtcDpRxCtlClockEn_t, DRV_ENTRY_FLAG, 1, 0},
        {CtcDpTxCtlClockEn_t, DRV_ENTRY_FLAG, 1, 0},
        {ProgramEgrAclTcamLowPowerCtl_t, DRV_ENTRY_FLAG, 1, 0},
        {ProgramIngAclTcamLowPowerCtl_t, DRV_ENTRY_FLAG, 1, 0},
        {CpuMacHssCmnCfg_t, CpuMacHssCmnCfg_cfgHssPowerupIVref_f, 1, 0},
        {HssCmnCfg_t, HssCmnCfg_cfgHssPowerupIVref_f, 40, 0}
    };

    if (!DRV_FROM_TMM(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }

    if (enable)
    {
        sal_memset(ds_zero, 0, sizeof(ds_zero));
        sal_memset(ds_set, 0xff, sizeof(ds_set));
    }
    else
    {
        sal_memset(ds_zero, 0xff, sizeof(ds_zero));
        sal_memset(ds_set, 0x0, sizeof(ds_set));
    }

    if (enable)
    {
        sys_usw_interrupt_set_group_en(lchip, FALSE);
    }

    if (DRV_IS_AT(lchip))
    {
        uint32 mc_mac_valid = 0;

        sys_usw_port_api_get_mac_group_valid(lchip,0, &mc_mac_valid);
        cmd = DRV_IOW(HssCmnCfg_t, HssCmnCfg_cfgHssPowerupIVref_f);
        for (num=0; num < 40; num++)
        {
            if (CTC_IS_BIT_SET(mc_mac_valid, num>>1))
            {
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, num, cmd, ds_zero));
            }
        }

        for(idx=0; idx< (sizeof(at_hibernate_tab)/sizeof(sys_usw_register_eco_tbl_t)-1); idx++)
        {
            cmd = DRV_IOW(at_hibernate_tab[idx].tbl_id, at_hibernate_tab[idx].fld_id);
            p_value = at_hibernate_tab[idx].value?ds_set:ds_zero;
            is_fld = (DRV_ENTRY_FLAG == at_hibernate_tab[idx].fld_id)?0:1;
            for (num=0; num<at_hibernate_tab[idx].num; num++)
            {
                if (0 == is_fld)
                {
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, num, cmd, p_value));
                }
                else
                {
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, num, cmd, p_value));
                }
            }
        } 
    }
    else
    {
        for(idx=0; idx< sizeof(hibernate_tab)/sizeof(sys_usw_register_eco_tbl_t); idx++)
        {
            cmd = DRV_IOW(hibernate_tab[idx].tbl_id, hibernate_tab[idx].fld_id);
            p_value = hibernate_tab[idx].value?ds_set:ds_zero;
            is_fld = (DRV_ENTRY_FLAG == hibernate_tab[idx].fld_id)?0:1;
            for (num=0; num<hibernate_tab[idx].num; num++)
            {
                if (0 == is_fld)
                {
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, num, cmd, p_value));
                }
                else
                {
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, num, cmd, p_value));
                }
            }
        }
    }
    return CTC_E_NONE;
}

int32
sys_usw_global_ctl_set(uint8 lchip, ctc_global_control_type_t type, void* value)
{
    uint32 field_val = 0;
    uint32 val = 0;
    uint32 enable = 0;
    uint32 chan_id = 0;
    uint32 cmd = 0;
    uint16 loop = 0;
    uint8 gchip = 0;
    uint8 ppid, dpid = 0;
    uint32 gport = 0;
    ds1_t   ds;
    MacsecRxCtl_m MacsecRxCtl;
    XSecRxDecryptDpCtl_m XSecRxDecryptDpCtl;
    EpeHeaderEditTruncationCtl_m truncationctl;
    ctc_parser_l2_protocol_entry_t parser_l2_entry;
    ctc_global_hmac_t* p_hmac = NULL;
    ctc_global_overlay_decap_mode_t* p_decap_mode = (ctc_global_overlay_decap_mode_t*)value;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    DmaFlushCtl_m flush_ctl;
    DmaPktRx0Ctl_m rx_ctl;

    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_REGISTER_INIT_CHECK;
    CTC_PTR_VALID_CHECK(value);

    switch(type)
    {
    case CTC_GLOBAL_LOGIC_PORT_ISOLATE_EN:
        field_val = (*(uint32 *)value)?1:0;
        cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_supportLogicPortIsolation_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_NPM_IM_EN:   /* TMM: support Mpls IM */
        {
        uint8 service_queue_mode = 0;
        uint32 ip_ecn = 0;
        uint32 im_bitmap = 0;
        im_bitmap = *(uint32 *)value;
        CTC_MAX_VALUE_CHECK(im_bitmap, CTC_GLOBAL_NPM_IM_MAX-1);
        
        if (!(DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)) && CTC_FLAG_ISSET(im_bitmap, CTC_GLOBAL_NPM_IM_MPLS))
        {
            return CTC_E_NOT_SUPPORT;
        }

        enable = CTC_FLAG_ISSET(im_bitmap, CTC_GLOBAL_NPM_IM_IP_ECN)?1:0;
        cmd = DRV_IOR(EpePktProcCtl_t, EpePktProcCtl_ecnIgnoreCheck_f);
        DRV_FIELD_IOCTL(lchip, 0, cmd, &ip_ecn);
        if (enable != ip_ecn)
        {
            sys_usw_queue_drop_ecn_init(lchip, enable);
        }

        if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
        {
            enable = CTC_FLAG_ISSET(im_bitmap, CTC_GLOBAL_NPM_IM_MPLS)?1:0;
            cmd = DRV_IOR(ParserMplsCtl_t, ParserMplsCtl_supportMplsInbandOam_f);
            DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val);
            if (field_val == enable)
            {
                return CTC_E_NONE;
            }
            CTC_ERROR_RETURN(sys_usw_queue_get_service_queue_mode(lchip, &service_queue_mode));
            if((1 == service_queue_mode) || !MCHIP_FEATURE_EN(lchip, CTC_FEATURE_IPFIX))
            {
                return CTC_E_NOT_SUPPORT;
            }
            CTC_ERROR_RETURN(SYS_CB(SYS_CB_NPM_IM_SET_EN, lchip, CTC_NPM_IM_TYPE_MPLS, enable));
            cmd = DRV_IOW(ParserMplsCtl_t, ParserMplsCtl_supportMplsInbandOam_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &enable));
            cmd = DRV_IOW(IpePreLookupCtl_t, IpePreLookupCtl_supportMplsInbandOam_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &enable));
            cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_mplsInBandOamEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &enable));
            cmd = DRV_IOW(EpeHdrAdjustCtl_t, EpeHdrAdjustCtl_mplsInBandOamEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &enable));
            cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_mplsInBandOamEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &enable));
            cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_supportExtLenCid_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &enable));
            cmd = DRV_IOW(EpeHdrAdjustCtl_t, EpeHdrAdjustCtl_supportExtLenCid_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &enable));
            cmd = DRV_IOW(EpeHeaderEditCtl_t, EpeHeaderEditCtl_supportExtLenCid_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &enable));
            cmd = DRV_IOW(EpeHeaderEditCtl_t, EpeHeaderEditCtl_toCpuWithCidExt_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &enable));
            enable = enable ? 0 : 1;
            cmd = DRV_IOW(IpeMplsCtl_t, IpeMplsCtl_entropyLabelTtlCheckEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &enable));
        }
        else if (DRV_IS_AT(lchip))
        {
            ParserIpCtl_m parser_ip_ctl;
            sys_com_npm_im_ip_t ip_info;
            uint32 ip_im = 0;
            cmd = DRV_IOR(ParserIpCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &parser_ip_ctl));

            if(GetParserIpCtl(V, ipv4ExtHdr0ProtocolEn_f, &parser_ip_ctl) && GetParserIpCtl(V, ipv4ExtHdr0Type_f, &parser_ip_ctl) == SYS_PARSER_L3_EXT_TYPE_IFA)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "ifa enable, im cannot enable\n");
                return CTC_E_NOT_SUPPORT;
            }
            sal_memset(&ip_info, 0, sizeof(sys_com_npm_im_ip_t));
            ip_im = GetParserIpCtl(V, ipv4ExtHdr1ProtocolEn_f, &parser_ip_ctl);
            /*arctic ip_ecn and ip all use xdata, so need to check*/
            if(MCHIP_XDATA(lchip)->func_en && (0 == ip_im) && (0 == ip_ecn) && CTC_FLAG_ISSET(im_bitmap, CTC_GLOBAL_NPM_IM_IP_ECN))
            {
                CTC_ERROR_RETURN(MCHIP_XDATA(lchip)->func_en(lchip, SYS_XDATA_FUNC_IP_IOAM, TRUE, NULL));
            }
            else if(MCHIP_XDATA(lchip)->func_en && ((1 == ip_im) || (1 == ip_ecn)) && !CTC_FLAG_ISSET(im_bitmap, CTC_GLOBAL_NPM_IM_IP_ECN))
            {
                CTC_ERROR_RETURN(MCHIP_XDATA(lchip)->func_en(lchip, SYS_XDATA_FUNC_IP_IOAM, FALSE, NULL));
            }
            CTC_ERROR_RETURN(SYS_CB(SYS_CB_NPM_IM_SET_EN, lchip, CTC_NPM_IM_TYPE_IPV4, 0));
            /*for ipv4*/
            SetParserIpCtl(V, ipv4ExtHdr1ProtocolEn_f, &parser_ip_ctl, 0);
            CTC_ERROR_RETURN(SYS_CB(SYS_CB_NPM_IM_GET_IP_INFO, lchip, &ip_info));
            SetParserIpCtl(V, ipv4ExtHdr1Protocol_f, &parser_ip_ctl, ip_info.im_proto);
            SetParserIpCtl(V, ipv4ExtHdr1Offset_f, &parser_ip_ctl, SYS_USW_IP_IM_NEXT_PROTOCOL_OFFSET_IPV4);
            SetParserIpCtl(V, ipv4Option1LenType_f, &parser_ip_ctl, 0);
            SetParserIpCtl(V, ipv4ExtHdr1Len_f, &parser_ip_ctl, SYS_USW_IP_IM_HEADER_LENGTH_IPV4);
            SetParserIpCtl(V, ipv4ExtHdr1Type_f, &parser_ip_ctl, 3);
            SetParserIpCtl(V, gL3ExtType_3_typeValue_f, &parser_ip_ctl, 6);

            /*for ipv6*/
            SetParserIpCtl(V, ipv6HopByHopExtType_f, &parser_ip_ctl, 3);
            SetParserIpCtl(V, gL3ExtType_7_typeValue_f, &parser_ip_ctl, 6);
            SetParserIpCtl(V, l3ExtDataEn_f, &parser_ip_ctl, 0x88);
            cmd = DRV_IOW(ParserIpCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &parser_ip_ctl));
            field_val = 0;
            cmd = DRV_IOW(ParserL3Ctl_t, ParserL3Ctl_hopByHopLenType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            field_val = 0x6;
            cmd = DRV_IOW(IpeRouteCtl_t, IpeRouteCtl_ipOptionsEscapeDisable_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            field_val = 0x0;
            cmd = DRV_IOW(IpeTunnelDecapCtl_t, IpeTunnelDecapCtl_ipOptionTunnelFatalException_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        }
        break;
    case CTC_GLOBAL_NPM_IM_LOSS_PROF_INTERVAL:
        if (DRV_FROM_AT(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        CTC_ERROR_RETURN(SYS_CB(SYS_CB_NPM_IM_SET_LOSS_PROFILE, lchip, (void*)value));
        break;
    case CTC_GLOBAL_ESLB_EN:   /* TMM: support MplsEvpn */
        if (DRV_FROM_TMM(lchip))
        {
            field_val = *(uint32 *)value ? 1 : 0;
            cmd = DRV_IOW(IpeMplsCtl_t, IpeMplsCtl_supportMplsEvpn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_supportMplsEvpn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            cmd = DRV_IOW(EpeHdrAdjustCtl_t, EpeHdrAdjustCtl_supportMplsEvpn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_supportMplsEvpn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            cmd = DRV_IOW(BufferStoreCtl_t, BufferStoreCtl_supportMplsEvpn_f);
            SYS_SET_FIELD_TBL_ALL_DP(lchip, cmd, field_val);
        }
        else if ((SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) && DRV_IS_TSINGMA(lchip))
        {
            field_val = (*(uint32*)value)?1:0;
            cmd = DRV_IOR(IpeIntfMapReserved_t, IpeIntfMapReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
            if (field_val)
            {
                CTC_SET_FLAG(val, 1<<1);
                CTC_SET_FLAG(val, IPEDISCARDTYPE_MPLS_ENTROPY_LABEL_CHK<<2);
            }
            else
            {
                CTC_UNSET_FLAG(val, 1<<1);
                CTC_UNSET_FLAG(val, IPEDISCARDTYPE_MPLS_ENTROPY_LABEL_CHK<<2);
            }
            cmd = DRV_IOW(IpeIntfMapReserved_t, IpeIntfMapReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
            cmd = DRV_IOR(IpeFwdReserved_t, IpeFwdReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
            if (field_val)
            {
                CTC_SET_FLAG(val, 1<<2);
            }
            else
            {
                CTC_UNSET_FLAG(val, 1<<2);
            }
            cmd = DRV_IOW(IpeFwdReserved_t, IpeFwdReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
            cmd = DRV_IOR(EpeNextHopReserved_t, EpeNextHopReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
            if (field_val)
            {
                CTC_SET_FLAG(val, 1<<3);
                CTC_SET_FLAG(val, 0x38 <<8);/*discard type*/
            }
            else
            {
                CTC_UNSET_FLAG(val, 1<<3);
                CTC_UNSET_FLAG(val, 0x38 <<8);/*discard type*/
            }
            cmd = DRV_IOW(EpeNextHopReserved_t, EpeNextHopReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
            cmd = DRV_IOR(EpeHdrProcReserved_t, EpeHdrProcReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
            if (field_val)
            {
                CTC_SET_FLAG(val, 1<<6);
                CTC_SET_FLAG(val, 1<<7);
            }
            else
            {
                CTC_UNSET_FLAG(val, 1<<6);
                CTC_UNSET_FLAG(val, 1<<7);
            }
            cmd = DRV_IOW(EpeHdrProcReserved_t, EpeHdrProcReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        }
        else
        {
            return CTC_E_NOT_SUPPORT;
        }
        if (field_val)
        {
            CTC_ERROR_RETURN(_sys_usw_global_set_eslb_en(lchip));
        }
        break;

    case CTC_GLOBAL_HMAC_EN:
        if(!MCHIP_SUB_FEATURE_CAP(lchip, SYS_FEATURE_HMAC))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(HMacEngineReserved_t, HMacEngineReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        if (0xFFFF == field_val)
        {
            SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [HMacEngineReserved.reserved] not support hmac en\n");
            return CTC_E_NOT_SUPPORT;
        }
        p_hmac = value;
        enable = p_hmac->enable ? 1 : 0;
        if (enable)
        {
            field_val = 1;
            cmd = DRV_IOW(HMacEngineInit_t, HMacEngineInit_init_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            #ifdef EMULATION_ENV
            sal_task_sleep(5000);
            #else
            sal_task_sleep(1);
            if (0 == SDK_WORK_PLATFORM)
            {
                cmd = DRV_IOR(HMacEngineInitDone_t, HMacEngineInitDone_initDone_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
                if (!field_val)
                {
                    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [HMacEngineInitDone.initDone] Feature not initialized \n");
                    return CTC_E_NOT_INIT;
                }
            }
            #endif
            cmd = DRV_IOR(CtcMiscCtlClkEn_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            SetCtcMiscCtlClkEn(V, enClkHMacEngine_f, ds, field_val);
            cmd = DRV_IOW(CtcMiscCtlClkEn_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        }
        sal_memset(ds, 0, sizeof(ds_t));
        cmd = DRV_IOR(ParserIpCtl_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, cmd, ds);
        if (GetParserIpCtl(V, ipv4ExtHdr0ProtocolEn_f, ds) && GetParserIpCtl(V, ipv4ExtHdr0Type_f, ds) != SYS_PARSER_L3_EXT_TYPE_SAP)
        {
            return CTC_E_INVALID_CONFIG;
        }

        SetParserIpCtl(V, ipv4ExtHdr0ProtocolEn_f, ds, enable);
        SetParserIpCtl(V, ipv4ExtHdr0Protocol_f, ds, enable? 215: 0);   /* sap is 215 */
        SetParserIpCtl(V, ipv4ExtHdr0Type_f, ds, enable? SYS_PARSER_L3_EXT_TYPE_SAP: 0);
        cmd = DRV_IOW(ParserIpCtl_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, cmd, ds);
        field_val = enable? SYS_PARSER_L3_EXT_TYPE_SAP: 0;
        cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_layer3ExtType_f);
        DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val);
        sal_memset(ds, 0, sizeof(ds_t));
        cmd = DRV_IOR(SclEngineCtl_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, cmd, ds);
        SetSclEngineCtl(V, hmacCheckUseHash0_f, ds, enable);
        SetSclEngineCtl(V, hmacCheckHash0LookupType_f, ds, enable? DRV_ENUM(DRV_USERIDHASHTYPE_IPV4PORT): 0);
        cmd = DRV_IOW(SclEngineCtl_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, cmd, ds);
        field_val = enable;
        cmd = DRV_IOW(IpeLoopbackHeaderAdjustCtl_t, IpeLoopbackHeaderAdjustCtl_hmacCheckEn_f);
        DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val);

        cmd = DRV_IOR(HmacEngineCtl_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, cmd, ds);
        SetHmacEngineCtl(V, hmacEn_f, ds, enable);
        SetHmacEngineCtl(V, ipProtocolReplaceEn_f, ds, p_hmac->ip_protocol_en? 1: 0);
        SetHmacEngineCtl(V, ipProtocolReplaceValue_f, ds, p_hmac->ip_protocol);
        SYS_USW_HMAC_SET_IP_HEADER_HW(p_hmac->ip_header_mask, CTC_IP_HEADER_LEN);
        SetHmacEngineCtl(A, ipHeaderMask_f, ds, p_hmac->ip_header_mask);
        cmd = DRV_IOW(HmacEngineCtl_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, cmd, ds);

        field_val = enable;
        cmd = DRV_IOW(BufStoreLoopChanEopErrChgEn_t, BufStoreLoopChanEopErrChgEn_loopChanEopErrChgEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd , &field_val));
        cmd = DRV_IOW(BufStoreLoopChanEopErrChgEn_t, BufStoreLoopChanEopErrChgEn_loopChanEopErrChgEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 1, cmd , &field_val));

        {/*Hmac cam*/
            /*uint8  skip_checksum = TRUE;*/
            sal_memset(ds, 0, sizeof(ds));
            if (enable)
            {
                SetHmacEngineCam(V, ipProtocol_0_value_f, ds, SYS_L4_PROTOCOL_IPV4_ICMP);
                SetHmacEngineCam(V, ipProtocol_0_checksumOffsetType_f, ds, 0);
                SetHmacEngineCam(V, ipProtocol_1_value_f, ds, SYS_L4_PROTOCOL_IPV6_ICMP);
                SetHmacEngineCam(V, ipProtocol_1_checksumOffsetType_f, ds, 0);
                SetHmacEngineCam(V, ipProtocol_2_value_f, ds, SYS_L4_PROTOCOL_GRE);
                SetHmacEngineCam(V, ipProtocol_2_checksumOffsetType_f, ds, 1);
                SetHmacEngineCam(V, ipProtocol_3_value_f, ds, SYS_L4_PROTOCOL_UDP);
                SetHmacEngineCam(V, ipProtocol_3_checksumOffsetType_f, ds, 2);
                SetHmacEngineCam(V, ipProtocol_4_value_f, ds, SYS_L4_PROTOCOL_TCP);
                SetHmacEngineCam(V, ipProtocol_4_checksumOffsetType_f, ds, 3);
            }
            cmd = DRV_IOW(HmacEngineCam_t, DRV_ENTRY_FLAG);
            DRV_IOCTL(lchip, 0, cmd, ds);
        }
        if (enable)
        {
            parser_l2_entry.addition_offset = 0;
            parser_l2_entry.l2_header_protocol = 0x8871;
            parser_l2_entry.l2_type = CTC_PARSER_L2_TYPE_ETH_V2;
            parser_l2_entry.l3_type = CTC_PARSER_L3_TYPE_IPV4;
            parser_l2_entry.mask = 0x1FFFFF;
            CTC_ERROR_RETURN(sys_usw_parser_mapping_l3_type_inner(lchip, 3, 0, SYS_PARSER_L3_EXT_TYPE_SAP, &parser_l2_entry));
        }
        else
        {
            sys_usw_parser_unmapping_l3_type(lchip, 3);
        }
        if (!enable)
        {
            field_val = 0;
            cmd = DRV_IOR(CtcMiscCtlClkEn_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            SetCtcMiscCtlClkEn(V, enClkHMacEngine_f, ds, field_val);
            cmd = DRV_IOW(CtcMiscCtlClkEn_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        }
        break;

    case CTC_GLOBAL_DISCARD_SAME_MACDASA_PKT:
        field_val = *(bool *)value ? 1 : 0;

        cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_discardSameMacAddr_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_discardSameMacAddr_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;

    case CTC_GLOBAL_DISCARD_SAME_IPDASA_PKT:
        field_val = *(bool *)value ? 1 : 0;

        cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_discardSameIpAddr_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        cmd = DRV_IOW(IpeRouteCtl_t, (DRV_FROM_AT(lchip) ? IpeRouteCtl_ipDaEqualSaDiscard_f : IpeRouteCtl_ipDaEqulSaDiscard_f));
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_discardSameIpAddr_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;

    case CTC_GLOBAL_DISCARD_TTL_0_PKT:
        field_val = *(bool *)value ? 1 : 0;

        sal_memset(ds, 0, sizeof(ds));
        cmd = DRV_IOR(EpePktProcCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetEpePktProcCtl(V, discardMplsTagTtl0_f, ds, field_val);
        SetEpePktProcCtl(V, discardMplsTtl0_f, ds, field_val);
        SetEpePktProcCtl(V, discardRouteTtl0_f, ds, field_val);
        SetEpePktProcCtl(V, discardTrillTtl0_f, ds, field_val);
        SetEpePktProcCtl(V, discardTunnelTtl0_f, ds, field_val);
        SetEpePktProcCtl(V, ofTtlFailDiscard_f, ds, field_val);
        cmd = DRV_IOW(EpePktProcCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        break;

    case CTC_GLOBAL_DISCARD_MCAST_SA_PKT:
        field_val = *(bool *)value ? 0 : 1;

        cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_allowMcastMacSa_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        break;

    case CTC_GLOBAL_ECMP_DLB_MODE:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, CTC_GLOBAL_ECMP_DLB_MODE_MAX - 1);

        if (CTC_GLOBAL_ECMP_DLB_MODE_ELEPHANT == *(uint32*)value)
        {
            field_val = 1;
        }
        else if (CTC_GLOBAL_ECMP_DLB_MODE_TCP == *(uint32*)value)
        {
            field_val = 3;
        }
        else if (CTC_GLOBAL_ECMP_DLB_MODE_ALL == *(uint32*)value)
        {
            field_val = 2;
        }

        cmd = DRV_IOW(IpeEcmpCtl_t, IpeEcmpCtl_dlbEnableMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;

    case CTC_GLOBAL_ECMP_REBALANCE_MODE:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, CTC_GLOBAL_ECMP_REBALANCE_MODE_MAX - 1);

        if (CTC_GLOBAL_ECMP_REBALANCE_MODE_NORMAL == *(uint32*)value)
        {
            field_val = 2;
        }
        else if (CTC_GLOBAL_ECMP_REBALANCE_MODE_FIRST == *(uint32*)value)
        {
            field_val = 0;
        }
        else if (CTC_GLOBAL_ECMP_REBALANCE_MODE_PACKET == *(uint32*)value)
        {
            field_val = 1;
        }
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOW(EcmpDlbEngineCtl_t, EcmpDlbEngineCtl_rebalanceMode_f);
        }
        else
        {
            cmd = DRV_IOW(DlbEngineCtl_t, DlbEngineCtl_rebalanceMode_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;

     case CTC_GLOBAL_ECMP_FLOW_AGING_INTERVAL:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 4294967);
        field_val = ((*(uint32*)value) * 250) & 0x3FFFFFFF;
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOW(EcmpDlbEngineTimerCtl_t, EcmpDlbEngineTimerCtl_cfgRefDivAgingRstPulse_f);
        }
        else
        {
            cmd = DRV_IOW(DlbEngineTimerCtl_t, DlbEngineTimerCtl_cfgRefDivAgingRstPulse_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;

    case CTC_GLOBAL_ECMP_FLOW_INACTIVE_INTERVAL:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 0xFFFFFFFF);

        /*per packet rebalance start*/
        field_val = *(uint32*)value ? 1 : 0;
        cmd = DRV_IOR(EcmpDlbEngineCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetEcmpDlbEngineCtl(V, reblanceJitterEnable_f, ds, field_val);
        cmd = DRV_IOW(EcmpDlbEngineCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

        field_val = *(uint32*)value ? 2 : 0;
        cmd = DRV_IOR(DlbEngineTimerCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetDlbEngineTimerCtl(V, flowInactiveTsThreshold_f, ds, field_val);
        cmd = DRV_IOW(DlbEngineTimerCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        /*per packet rebalance end*/

        field_val = ((*(uint32*)value) >> 3) & 0x3FFFFFFF;
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOW(EcmpDlbEngineTimerCtl_t, EcmpDlbEngineTimerCtl_cfgRefDivInactiveRstPulse_f);
        }
        else
        {
            cmd = DRV_IOW(DlbEngineTimerCtl_t, DlbEngineTimerCtl_cfgRefDivInactiveRstPulse_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;

    case CTC_GLOBAL_ECMP_FLOW_PKT_INTERVAL:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 0xFFFF);

        if((*(uint32*)value) <= 256)        /* every 256 packets */
        {
            field_val = 1;
        }
        else if((*(uint32*)value) <= 1024)  /* every 1024 packets */
        {
            field_val = 0;
        }
        else if((*(uint32*)value) <= 8192)  /* every 8192 packets */
        {
            field_val = 2;
        }
        else                                 /* every 32768 packets */
        {
            field_val = 3;
        }
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOW(EcmpDlbEngineCtl_t, EcmpDlbEngineCtl_reorderPktIntervalMode_f);
        }
        else
        {
            cmd = DRV_IOW(DlbEngineCtl_t, DlbEngineCtl_reorderPktIntervalMode_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_SPM_AGING_INTERVAL:

        if (DRV_FROM_TMM(lchip))
        {
            /* set aging enable & scan enable & aging interval & antFlowAgingValid */
            uint8 is_enable = 0;
            sal_memset(ds, 0, sizeof(ds));

            is_enable = *((uint32*)value) ? 1 : 0;

            if (is_enable)
            {
                CTC_ERROR_RETURN(sys_usw_aging_set_aging_interval(lchip, SYS_AGING_TIMER_INDEX_RSV, *((uint32*)value)));
            }
            if (DRV_FROM_AT(lchip))
            {
                cmd = DRV_IOR(PpAgingCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

                SetPpAgingCtl(V, gTimmer_1_agingEn_f, ds, is_enable ? 1 : 0);
                SetPpAgingCtl(V, gTimmer_1_scanEn_f, ds, is_enable ? 1 : 0);
                SetPpAgingCtl(V, antFlowAgingValid_f, ds, is_enable ? 1 : 0);

                cmd = DRV_IOW(PpAgingCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            }
            else
            {
                cmd = DRV_IOR(IpeAgingCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

                SetIpeAgingCtl(V, gTimmer_1_agingEn_f, ds, is_enable ? 1 : 0);
                SetIpeAgingCtl(V, gTimmer_1_scanEn_f, ds, is_enable ? 1 : 0);
                SetIpeAgingCtl(V, antFlowAgingValid_f, ds, is_enable ? 1 : 0);

                cmd = DRV_IOW(IpeAgingCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            }
        }
        break;

    case CTC_GLOBAL_LINKAGG_FLOW_INACTIVE_INTERVAL:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 0xFF);
        field_val = (*(uint32*)value);
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOW(LagEngineTimerCtl_t, LagEngineTimerCtl_tsThreshold_f);
        }
        else
        {
            cmd = DRV_IOW(LagEngineTimerCtl0_t, LagEngineTimerCtl0_tsThreshold0_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_STACKING_TRUNK_FLOW_INACTIVE_INTERVAL:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 0xFF);
        field_val = (*(uint32*)value);
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOW(LagEngineTimerCtl_t, LagEngineTimerCtl_tsThreshold_f);
        }
        else
        {
            cmd = DRV_IOW(LagEngineTimerCtl1_t, LagEngineTimerCtl1_tsThreshold1_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_LAG_DLB_PROPERTY:
        if ((NULL == MCHIP_LAG(lchip)) || (NULL == MCHIP_LAG(lchip)->dlb_set_cfg))
        {
            return CTC_E_NOT_SUPPORT;
        }
        CTC_ERROR_RETURN(MCHIP_LAG(lchip)->dlb_set_cfg(lchip, value));
        break;
    case CTC_GLOBAL_WARMBOOT_STATUS:               /**< [D2] set warmboot status */
        drv_set_warmboot_status(lchip, *(uint32*)value);
        if (*(uint32*)value == CTC_WB_STATUS_DONE)
        {
            /*enable interrupt*/
            sys_usw_interrupt_set_group_en(lchip, TRUE);

            /*enable failover after warmboot done*/
            sys_usw_global_failover_en(lchip, TRUE);
        }else if (*(uint32*)value == CTC_WB_STATUS_SYNC)
        {
            CTC_ERROR_RETURN(_sys_usw_set_warmboot_sync(lchip));
        }
        break;

    case CTC_GLOBAL_WARMBOOT_CPU_RX_EN:
        enable = *(uint32 *)value ? 1 : 0;

        CTC_ERROR_RETURN(sys_usw_dma_knet_reset_en(lchip, ((*(uint32*)value==2)?0:1)));
        SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MASTER, 1);

        /*Bedore disable dma channel, should set dma flush en */
        if (enable)
        {
            sal_memset(&flush_ctl, 0, sizeof(flush_ctl));
        }
        else
        {
            sal_memset(&flush_ctl, 0xff, sizeof(flush_ctl));
        }
        cmd = DRV_IOW(DmaFlushCtl_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, cmd, &flush_ctl);
        if (DRV_IS_AT(lchip))
        {
            uint32 rx_tbl_id[] = {DmaPktRx0Ctl_t, DmaPktRx1Ctl_t, DmaPktRx2Ctl_t, DmaPktRx3Ctl_t, DmaPktRx4Ctl_t, DmaPktRx5Ctl_t, DmaPktRx6Ctl_t, DmaPktRx7Ctl_t};
            for(chan_id = 0; chan_id < SYS_DMA_PACKET_TX0_CHAN_ID; chan_id++)
            {
                cmd = DRV_IOR(rx_tbl_id[chan_id], DRV_ENTRY_FLAG);
                DRV_IOCTL(lchip, 0, cmd, &rx_ctl);
                SetDmaPktRx0Ctl(V, dmaPktRxFlushEn_f, &rx_ctl, enable ? 0:1);
                cmd = DRV_IOW(rx_tbl_id[chan_id], DRV_ENTRY_FLAG);
                DRV_IOCTL(lchip, 0, cmd, &rx_ctl);
            }
        }

        for(chan_id = 0; chan_id <= MCHIP_CAP(SYS_CAP_DMA_MAX_CHAN_ID); chan_id++)
        {
            if(chan_id == SYS_DMA_TBL_RD_CHAN_ID || chan_id == SYS_DMA_HASHKEY_CHAN_ID)
            {
                continue;
            }
            CTC_ERROR_RETURN(sys_usw_dma_set_chan_en(lchip, chan_id, enable));
        }

        CTC_ERROR_RETURN(sys_usw_interrupt_set_group_en(lchip, enable));
        p_usw_register_master[lchip]->wb_keep_knet = ((*(uint32*)value==2)?1:0);
        SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MASTER, 1);
        break;
    case CTC_GLOBAL_DISCARD_TCP_SYN_0_PKT:
        field_val = (*(bool*)value);
        cmd = DRV_IOR(ParserLayer4AppCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        field_val = field_val?(GetParserLayer4AppCtl(V, tcpFragCheck_f, ds) | 0x4) : (GetParserLayer4AppCtl(V, tcpFragCheck_f, ds) & 0xb);
        SetParserLayer4AppCtl(V, tcpFragCheck_f, ds, field_val);
        cmd = DRV_IOW(ParserLayer4AppCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        break;
    case CTC_GLOBAL_DISCARD_TCP_NULL_PKT:
    case CTC_GLOBAL_DISCARD_TCP_XMAS_PKT:
    case CTC_GLOBAL_DISCARD_TCP_SYN_FIN_PKT:
    case CTC_GLOBAL_DISCARD_SAME_L4_PORT_PKT:
    case CTC_GLOBAL_DISCARD_ICMP_FRAG_PKT:
        CTC_ERROR_RETURN(_sys_usw_global_ctl_l4_check_en(lchip, type, ((bool*)value), 1));
        break;

    case CTC_GLOBAL_ARP_MACDA_CHECK_EN:
    case CTC_GLOBAL_ARP_MACSA_CHECK_EN:
    case CTC_GLOBAL_ARP_IP_CHECK_EN:
    case CTC_GLOBAL_ARP_CHECK_FAIL_TO_CPU:
    case CTC_GLOBAL_GRATUITOUS_ARP_TO_CPU:
    case CTC_GLOBAL_ARP_LOCAL_CHECK_EN:
        field_val = (*(bool*)value)?1:0;
        CTC_ERROR_RETURN(_sys_usw_global_ctl_set_arp_check_en(lchip, type, ((uint32*)&field_val)));
        break;
   case CTC_GLOBAL_IGMP_SNOOPING_MODE:
        CTC_ERROR_RETURN(_sys_usw_global_ctl_set_igmp_mode(lchip, type, ((uint32*)value)));
        break;

    case CTC_GLOBAL_FLOW_PROPERTY:
        CTC_ERROR_RETURN(_sys_usw_set_glb_flow_property(lchip, (ctc_global_flow_property_t*)value));
        break;

    case CTC_GLOBAL_ACL_LKUP_PROPERTY:
        CTC_ERROR_RETURN(_sys_usw_set_glb_acl_lkup_property(lchip, (ctc_acl_property_t*)value));
        break;
    case CTC_GLOBAL_ELOOP_USE_LOGIC_DESTPORT:
        field_val = (*(bool*)value)?1:0;
        cmd = DRV_IOW(EpeHeaderEditCtl_t, EpeHeaderEditCtl_ingressEditUseLogicPortSelect_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_ACL_PROPERTY:
        CTC_ERROR_RETURN(sys_usw_set_glb_acl_property(lchip, (ctc_global_acl_property_t*)value, 0));
        break;
    case CTC_GLOBAL_SCL_PROPERTY:
        CTC_ERROR_RETURN(_sys_usw_set_glb_scl_property(lchip, (ctc_global_scl_property_t*)value));
        break;
    case CTC_GLOBAL_PIM_SNOOPING_MODE:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 1);
        field_val = *(uint32 *)value ? 0 : 1;
        cmd = DRV_IOW(IpeLookupCtl_t, IpeLookupCtl_pimSnoopingEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_IPMC_PROPERTY:
        CTC_ERROR_RETURN(_sys_usw_set_glb_ipmc_property(lchip, (ctc_global_ipmc_property_t*)value));
        break;

    case CTC_GLOBAL_CID_PROPERTY:
        CTC_ERROR_RETURN(_sys_usw_set_glb_cid_property(lchip, (ctc_global_cid_property_t*)value));
        break;

    case CTC_GLOBAL_VXLAN_UDP_DEST_PORT:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 0xFFFF);
        field_val = *(uint32*)value;
        if (0 == field_val)
        {
            field_val = 4789;
        }
        if (DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOR(XSecRxDecryptDpCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &XSecRxDecryptDpCtl));
            SetXSecRxDecryptDpCtl(V, ctcSecUdpPortDecrypted_f, &XSecRxDecryptDpCtl, field_val);
            cmd = DRV_IOW(XSecRxDecryptDpCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &XSecRxDecryptDpCtl));
        }
        if(DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(EpePktProcVxlanRsvCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

            SetEpePktProcVxlanRsvCtl(V, g_0_udpDestPort_f, &ds, field_val);
            cmd = DRV_IOW(EpePktProcVxlanRsvCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            if (DRV_FROM_AT(lchip))
            {
                for (ppid = lchip; ppid < lchip + SYS_PP_NUM(lchip); ppid++)
                {
                    for (dpid = 0; dpid < 2; dpid++)
                    {
                        cmd = DRV_IOR(XSecRxDecryptDpCtl_t, DRV_ENTRY_FLAG);
                        CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
                        SetXSecRxDecryptDpCtl(V, ctcSecUdpPortDecrypted_f, &ds, field_val);
                        cmd = DRV_IOW(XSecRxDecryptDpCtl_t, DRV_ENTRY_FLAG);
                        CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
                    }
                }
            }
            else
            {
                cmd = DRV_IOR(MacsecRxCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &MacsecRxCtl));
                SetMacsecRxCtl(V, cloudSecPlainUdpDestPort_f, &MacsecRxCtl, field_val);
                cmd = DRV_IOW(MacsecRxCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &MacsecRxCtl));
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(1, 0), cmd, &MacsecRxCtl));
            }
        }
        else
        {
            cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_vxlanV4UdpDestPort_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_vxlanV6UdpDestPort_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        cmd = DRV_IOW(ParserLayer4AppCtl_t, ParserLayer4AppCtl_vxlanUdpDestPort_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        cmd = DRV_IOW(ParserLayer4AppCtl_t, ParserLayer4AppCtl_evxlanUdpDestPort_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        cmd = DRV_IOW(ParserLayer4AppCtl_t, ParserLayer4AppCtl_decryptVxlanUdpDestPort_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_GENEVE_UDP_DEST_PORT:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 0xFFFF);
        field_val = *(uint32*)value;
        if (0 == field_val)
        {
            field_val = 6081;
        }
        if(!DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_geneveV4UdpDestPort_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_geneveV6UdpDestPort_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        cmd = DRV_IOW(ParserLayer4AppCtl_t, ParserLayer4AppCtl_geneveVxlanUdpDestPort_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_NH_FORCE_BRIDGE_DISABLE:
        field_val = (*(bool*)value)?0:1;
        cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_forceBridgeL3Match_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_NH_MCAST_LOGIC_REP_EN:
        enable = *(bool *)value ? 1 : 0;
        CTC_ERROR_RETURN(sys_usw_nh_set_ipmc_logic_replication(lchip, enable));
        break;

    case CTC_GLOBAL_LB_HASH_KEY:
        if ((NULL == MCHIP_HASH(lchip)) || (NULL == MCHIP_HASH(lchip)->set_cfg))
        {
            return CTC_E_NOT_SUPPORT;
        }
        CTC_ERROR_RETURN(MCHIP_HASH(lchip)->set_cfg(lchip, value));
        break;
    case CTC_GLOBAL_LB_HASH_OFFSET_PROFILE:
        if ((NULL == MCHIP_HASH(lchip)) || (NULL == MCHIP_HASH(lchip)->set_offset))
        {
            return CTC_E_NOT_SUPPORT;
        }
        CTC_ERROR_RETURN(MCHIP_HASH(lchip)->set_offset(lchip, value));

        break;
    case CTC_GLOBAL_OAM_POLICER_EN:
        val = (*(bool*)value)?0:1;
        if (DRV_IS_DUET2(lchip))
        {
            cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_oamBypassPolicingOp_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
            cmd = DRV_IOR(IpeFwdReserved_t, IpeFwdReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            val ? CTC_BIT_SET(field_val, 0) : CTC_BIT_UNSET(field_val, 0);
            cmd = DRV_IOW(IpeFwdReserved_t, IpeFwdReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            cmd = DRV_IOW(EpeClassficationCtl_t, EpeClassficationCtl_oamBypassPolicingOp_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
            cmd = DRV_IOR(EpeAclOamReserved_t, EpeAclOamReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            val ? CTC_BIT_SET(field_val, 0) : CTC_BIT_UNSET(field_val, 0);
            cmd = DRV_IOW(EpeAclOamReserved_t, EpeAclOamReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        else
        {
            cmd = DRV_IOW(IpeAclQosCtl_t, IpeAclQosCtl_oamBypassPolicingOp_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
            cmd = DRV_IOW(IpeAclQosCtl_t, IpeAclQosCtl_fromCpuOrOamBypassPolicing_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
            cmd = DRV_IOW(EpeClassficationCtl_t, EpeClassficationCtl_oamBypassPolicingOp_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
            cmd = DRV_IOW(EpeClassficationCtl_t, EpeClassficationCtl_fromCpuOrOamBypassPolicing_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        }

        cmd = DRV_IOW(EpeClassficationCtl_t, EpeClassficationCtl_oamBypassPolicingOp_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        if (DRV_IS_DUET2(lchip))
        {
            cmd = DRV_IOR(EpeAclOamReserved_t, EpeAclOamReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            val ? CTC_BIT_SET(field_val, 0) : CTC_BIT_UNSET(field_val, 0);
            cmd = DRV_IOW(EpeAclOamReserved_t, EpeAclOamReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        break;
    case CTC_GLOBAL_PARSER_OUTER_ALWAYS_CVLAN_EN:
        field_val = (*(bool*)value)? 1 : 0;
        cmd = DRV_IOW(ParserEthernetCtl_t, ParserEthernetCtl_outerAlwaysCvlan_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_VPWS_SNOOPING_PARSER:
        val = (*(bool *)value) ? 1 : 0;
        cmd = DRV_IOW(IpeTunnelIdCtl_t, IpeTunnelIdCtl_vpwsDecapsForceSecondParser_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        break;
    case CTC_GLOBAL_ARP_VLAN_CLASS_EN:
        field_val = (*(bool*)value)? 1 : 0;
        cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_arpForceIpv4_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        cmd = DRV_IOW(UserIdCtl_t, UserIdCtl_arpForceIpv4_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        cmd = DRV_IOW(UserIdCtl_t, UserIdCtl_arpForceIpv4Da_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_DISCARD_MACSA_0_PKT:
        field_val = *(bool *)value ? 1 : 0;
        cmd = DRV_IOW(IpeIntfMapperCtl_t, IpeIntfMapperCtl_discardAllZeroMacSa_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_NH_ARP_MACDA_DERIVE_MODE:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, CTC_GLOBAL_MACDA_DERIVE_FROM_NH_ROUTE2);
        SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MASTER, 1);

        field_val = (*(uint32*)value)? 1 : 0;
        cmd = DRV_IOW(EpeHdrAdjustCtl_t, EpeHdrAdjustCtl_hostRouteNextHopSaveEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_hostRouteNextHopSaveEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));


        field_val = (*(uint32*)value == CTC_GLOBAL_MACDA_DERIVE_FROM_NH_ROUTE2)? 0 : 1;
        cmd = DRV_IOW(IpeRouteCtl_t, IpeRouteCtl_cloudSecUseShareBit_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        /*cfg derive mode*/
        field_val = *(uint32*)value;
        cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_hostRouteNextHopSaveMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        p_usw_register_master[lchip]->derive_mode = *(uint32*)value;
        SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MASTER, 1);
        break;
    case CTC_GLOBAL_VXLAN_CRYPT_UDP_DEST_PORT:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 0xffff);
        field_val = *(uint32*)value;

        if (DRV_FROM_AT(lchip))
        {
            for (ppid = lchip; ppid < lchip + SYS_PP_NUM(lchip); ppid++)
            {
                for (dpid = 0; dpid < 2; dpid++)
                {
                    cmd = DRV_IOR(XSecTxEncryptDpCtl_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
                    SetXSecTxEncryptDpCtl(V, ctcSecUdpPort_f, &ds, field_val);
                    cmd = DRV_IOW(XSecTxEncryptDpCtl_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));

                    cmd = DRV_IOR(XSecRxParserDpCtl_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
                    SetXSecRxParserDpCtl(V, ctcSecUdpPort_f, &ds, field_val);
                    cmd = DRV_IOW(XSecRxParserDpCtl_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
                }
            }
        }
        else if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
        {
            cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_cloudSecUdpPort_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            cmd = DRV_IOW(MacsecTxCtl_t, MacsecTxCtl_cloudSecUdpDestPort_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 1, cmd, &field_val));
        }
        else
        {
            cmd = DRV_IOW(ParserLayer4AppCtl_t, ParserLayer4AppCtl_encryptVxlanUdpDestPort_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_encryptVxlanUdpDestPort_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        break;
    case CTC_GLOBAL_DOT1AE_CRYPT_CTCSH_UDP_DEST_PORT:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 0xffff);
        field_val = *(uint32*)value;

        for (ppid = lchip; ppid < lchip + SYS_PP_NUM(lchip); ppid++)
        {
            for (dpid = 0; dpid < 2; dpid++)
            {
                cmd = DRV_IOR(XSecTxEncryptDpCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
                SetXSecTxEncryptDpCtl(V, ctcSecShimUdpPort_f, &ds, field_val);
                cmd = DRV_IOW(XSecTxEncryptDpCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));

                cmd = DRV_IOR(XSecRxParserDpCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
                SetXSecRxParserDpCtl(V, ctcSecShimUdpPort_f, &ds, field_val);
                cmd = DRV_IOW(XSecRxParserDpCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
            }
        }
        break;
    case CTC_GLOBAL_DOT1AE_CRYPT_IP_PROTOCOL:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 0xff);
        field_val = *(uint32*)value;

        for (ppid = lchip; ppid < lchip + SYS_PP_NUM(lchip); ppid++)
        {
            for (dpid = 0; dpid < 2; dpid++)
            {
                cmd = DRV_IOR(XSecTxEncryptDpCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
                SetXSecTxEncryptDpCtl(V, ctcSecIpProtocol_f, &ds, field_val);
                cmd = DRV_IOW(XSecTxEncryptDpCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));

                cmd = DRV_IOR(XSecRxParserDpCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
                SetXSecRxParserDpCtl(V, ipCtcSecProtocol_f, &ds, field_val);
                cmd = DRV_IOW(XSecRxParserDpCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
            }
        }
        break;
    case CTC_GLOBAL_DOT1AE_CRYPT_CTCSH_IP_PROTOCOL:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 0xff);
        field_val = *(uint32*)value;

        for (ppid = lchip; ppid < lchip + SYS_PP_NUM(lchip); ppid++)
        {
            for (dpid = 0; dpid < 2; dpid++)
            {
                cmd = DRV_IOR(XSecTxEncryptDpCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
                SetXSecTxEncryptDpCtl(V, ctcSecShimIpProtocol_f, &ds, field_val);
                cmd = DRV_IOW(XSecTxEncryptDpCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));

                cmd = DRV_IOR(XSecRxParserDpCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
                SetXSecRxParserDpCtl(V, ipCtcSecShimProtocol_f, &ds, field_val);
                cmd = DRV_IOW(XSecRxParserDpCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(ppid, 0, DRV_CMD_DP_EN(cmd, dpid), &ds));
            }
        }
        break;
    case CTC_GLOBAL_TPOAM_VPWSOAM_COEXIST:
        if (!DRV_IS_DUET2(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        field_val = *(uint32 *)value ? 1 : 0;
        p_usw_register_master[lchip]->tpoam_vpws_coexist = field_val;
        SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MASTER, 1);
        break;
    case CTC_GLOBAL_VXLAN_POLICER_GROUP_ID_BASE:
        if (DRV_FROM_TMM(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        CTC_MAX_VALUE_CHECK(*(uint32*)value, 0xff00);
        field_val = *(uint32*)value;
        cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_vxlanPolicyGidBase_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_INBAND_CPU_TRAFFIC_TIMER:
        return CTC_E_NOT_SUPPORT;
    case CTC_GLOBAL_DUMP_DB:
        CTC_ERROR_RETURN(_sys_usw_set_dump_db(lchip, (ctc_global_dump_db_t*)value));
        break;
    case CTC_GLOBAL_IGS_RANDOM_LOG_SHIFT:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, DRV_FROM_TMM(lchip)? 15: 7);
        field_val = *(uint32*)value;
        cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_randomLogShift_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        MCHIP_CAP(SYS_CAP_RANDOM_LOG_SHIFT) = field_val;
        break;
    case CTC_GLOBAL_EGS_RANDOM_LOG_SHIFT:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, DRV_FROM_TMM(lchip)? 15: 7);
        field_val = *(uint32*)value;
        cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_randomLogShift_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        MCHIP_CAP(SYS_CAP_RANDOM_LOG_EGS_SHIFT) = field_val;
        break;
    case CTC_GLOBAL_OVERLAY_DECAP_MODE:
        CTC_MAX_VALUE_CHECK(p_decap_mode->scl_id, 1);
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOW(UserIdCtl_t, (p_decap_mode->scl_id)? UserIdCtl_vxlanTunnelHash1LkpMode_f: UserIdCtl_vxlanTunnelHash0LkpMode_f);
        }
        else
        {
            cmd = DRV_IOW(IpeUserIdCtl_t, DRV_IS_DUET2(lchip) ? \
                ((p_decap_mode->scl_id)? IpeUserIdCtl_vxlanTunnelHash2LkpMode_f: IpeUserIdCtl_vxlanTunnelHash1LkpMode_f):\
                ((p_decap_mode->scl_id)? IpeUserIdCtl_vxlanTunnelHash1LkpMode_f: IpeUserIdCtl_vxlanTunnelHash0LkpMode_f));
        }
        field_val = p_decap_mode->vxlan_mode ? 0:1;
        CTC_ERROR_RETURN(sys_usw_scl_set_vxlan_lookup(lchip, p_decap_mode->vxlan_mode));
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOW(UserIdCtl_t, (p_decap_mode->scl_id)? UserIdCtl_nvgreTunnelHash1LkpMode_f: UserIdCtl_nvgreTunnelHash0LkpMode_f);
        }
        else
        {
            cmd = DRV_IOW(IpeUserIdCtl_t, DRV_IS_DUET2(lchip) ? \
                ((p_decap_mode->scl_id)? IpeUserIdCtl_nvgreTunnelHash2LkpMode_f: IpeUserIdCtl_nvgreTunnelHash1LkpMode_f):
                ((p_decap_mode->scl_id)? IpeUserIdCtl_nvgreTunnelHash1LkpMode_f: IpeUserIdCtl_nvgreTunnelHash0LkpMode_f));
        }
        field_val = p_decap_mode->nvgre_mode ? 0:1;
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        if(p_decap_mode->nvgre_mode || p_decap_mode->vxlan_mode)
        {
            field_val = 1;
            cmd = DRV_IOW(SclEngineCtl_t, SclEngineCtl_array_0_disableHash1IpSaType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        break;
    case CTC_GLOBAL_EGS_STK_ACL_DIS:
        cmd = DRV_IOW(EpeAclQosCtl_t, EpeAclQosCtl_stackingDisableAcl_f);
        field_val = (*(bool*)value)? 1:0;
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
   case CTC_GLOBAL_STK_WITH_IGS_PKT_HDR_EN:
        cmd = DRV_IOW(EpeHdrAdjustCtl_t, EpeHdrAdjustCtl_toRemoteCpuAttachHeader_f);
        field_val = (*(bool*)value)? 1:0;
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        CTC_ERROR_RETURN(sys_usw_packet_tx_set_property(lchip, SYS_PKT_TX_TYPE_STK_INNER_BRG_EN, field_val, 0));
        break;
    case CTC_GLOBAL_NET_RX_EN:
        field_val = (*(uint32*)value)? 1:0;
        CTC_ERROR_RETURN(_sys_usw_global_net_rx_enable(lchip, field_val));
        break;
    case CTC_GLOBAL_EACL_SWITCH_ID:
        if (0 == ((SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) && DRV_IS_TSINGMA(lchip)))
        {
            return CTC_E_NOT_SUPPORT;
        }
        field_val = (0xFFFF != *(uint32*)value)?1:0;
        if (field_val)
        {
            CTC_MAX_VALUE_CHECK(*(uint32*)value, 1023);
        }
        cmd = DRV_IOW(IpeAclQosCtl_t, IpeAclQosCtl_privateIntEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_privateIntEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        cmd = DRV_IOR(EpeHdrEditReserved_t, EpeHdrEditReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        if (field_val)
        {
            CTC_BIT_SET(val, 1);
        }
        else
        {
            CTC_BIT_UNSET(val, 1);
        }
        cmd = DRV_IOW(EpeHdrEditReserved_t, EpeHdrEditReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        cmd = DRV_IOR(EpeScheduleReserved_t, EpeScheduleReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &val));
        if (field_val)
        {
            CTC_BIT_SET(val, 0);
        }
        else
        {
            CTC_BIT_UNSET(val, 0);
        }

        CTC_UNSET_FLAG(val, 0x7FE);
        field_val = (*(uint32*)value) & 0x3FF;
        CTC_SET_FLAG(val, field_val<<1);
        cmd = DRV_IOW(EpeScheduleReserved_t, EpeScheduleReserved_reserved_f);
        SYS_SET_FIELD_TBL_ALL_DP(lchip, cmd, val);
        field_val = (0xFFFF != *(uint32*)value)?1:0;
        sys_usw_get_gchip_id(lchip, &gchip);
        for(loop=0; loop < MCHIP_CAP(SYS_CAP_SPEC_MAX_PHY_PORT_NUM); loop++)
        {
            gport = CTC_MAP_LPORT_TO_GPORT(gchip, loop);
            dmps_port_info.gport = gport;
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
            if (SYS_COMMON_USELESS_CHANNEL == chan_id)
            {
                continue;
            }
            sys_usw_dmps_set_port_property(lchip, gport, SYS_PORT_API_DMPS_PROP_TX_PRIVATE_INT_EN, &field_val);
        }
        break;
    case CTC_GLOBAL_FLOW_RECORDER_EN:
        {
            ctc_global_flow_recorder_t* p_flow_recorder = (ctc_global_flow_recorder_t*)value;

            cmd = DRV_IOR(IpeFlowHashCtl_t, IpeFlowHashCtl_igrIpfix32KMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            if(field_val)
            {
                return CTC_E_NONE;
            }
            field_val = 1;
            cmd = DRV_IOW(IpeFlowHashCtl_t, IpeFlowHashCtl_igrIpfix32KMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_igrIpfix32KMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            cmd = DRV_IOW(GlobalStatsCtl_t, GlobalStatsCtl_igrIpfix32KMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            cmd = DRV_IOW(FlowHashCtl_t, FlowHashCtl_igrIpfix32KMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

            field_val = p_flow_recorder->resolve_conflict_en?1:0;
            cmd = DRV_IOW(IpeAclQosCtl_t, IpeAclQosCtl_igrIpfix32KModeEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

            field_val = p_flow_recorder->resolve_conflict_level;
            cmd = DRV_IOW(IpeAclQosCtl_t, IpeAclQosCtl_igrIpfix32KModeAclLevel_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

            field_val = p_flow_recorder->queue_drop_stats_en;
            cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_queueDropCheckEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

            field_val = 0xFFFFFFFE;
            cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_ipfix32KModeCareDiscardType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            CTC_ERROR_RETURN(sys_usw_acl_set_global_cfg(lchip, 1, 1));
            if (p_flow_recorder->queue_drop_stats_en)
            {
                uint8 gchipid = 0;
                uint8 mcast;
                uint8 priority;
                uint8 index;
                uint8 color;
                DsErmPrioScTcMap_m erm_prio_sc_tc_map;
                DsErmColorDpMap_m erm_color_dp_map;
                uint32 chan[2];
                ctc_internal_port_assign_para_t port_assign;
                ctc_qos_glb_cfg_t global_cfg;
                sal_memset(&port_assign, 0, sizeof(port_assign));

                /*alloc iloop port for span on drop stats*/
                sys_usw_get_gchip_id(lchip, &gchipid);
                port_assign.type = CTC_INTERNAL_PORT_TYPE_ILOOP;
                port_assign.gchip = gchipid;
                CTC_ERROR_RETURN(sys_usw_internal_port_allocate(lchip, &port_assign));

                field_val = port_assign.inter_port;
                cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_queueDropLpbkUseInternalPort_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

                CTC_ERROR_RETURN(sys_usw_port_api_set_property(lchip, CTC_MAP_LPORT_TO_GPORT(gchipid, field_val), CTC_PORT_PROP_CROSS_CONNECT_EN, 1))
                /*
                Because of RTL limitation, span on drop packet can not coexist with normal packet on the same queue.
                Normal packet pass through the first 4 queues and span on drop packet pass through another queue.
                */
                for (mcast = 0; mcast < 2; mcast++)
                {
                    for (priority = 0; priority < 16; priority++)
                    {
                        index = mcast << 4 | priority;

                        cmd = DRV_IOR(DsErmPrioScTcMap_t, DRV_ENTRY_FLAG);
                        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &erm_prio_sc_tc_map));
                        SetDsErmPrioScTcMap(V, g2_3_mappedTc_f, &erm_prio_sc_tc_map, priority / 4);
                        cmd = DRV_IOW(DsErmPrioScTcMap_t, DRV_ENTRY_FLAG);
                        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &erm_prio_sc_tc_map));
                    }
                }
                for (mcast = 0; mcast < 2; mcast++)
                {
                    for (color = 0; color < 4; color++)
                    {
                        index = mcast << 2 | color;
                        field_val = mcast ? 0 : ((color + 3) % 4);
                        cmd = DRV_IOR(DsErmColorDpMap_t, DRV_ENTRY_FLAG);
                        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &erm_color_dp_map));
                        SetDsErmColorDpMap(V, g_3_dropPrecedence_f, &erm_color_dp_map, field_val);
                        cmd = DRV_IOW(DsErmColorDpMap_t, DRV_ENTRY_FLAG);
                        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &erm_color_dp_map));
                    }
                }
                field_val = 3;
                cmd = DRV_IOW(DsErmChannel_t, DsErmChannel_ermProfId_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, MCHIP_CAP(SYS_CAP_CHANID_ILOOP), cmd, &field_val));

                sal_memset(&global_cfg, 0, sizeof(global_cfg));
                global_cfg.cfg_type = CTC_QOS_GLB_CFG_QUEUE_DROP_MONITOR_EN;
                global_cfg.u.drop_monitor.src_gport = 1;
                global_cfg.u.drop_monitor.dst_gport = 3;
                global_cfg.u.drop_monitor.enable = 1;
                CTC_ERROR_RETURN(sys_usw_qos_set_global_config(lchip,  &global_cfg));

                sal_memset(&ds, 0, sizeof(ds));
                sal_memset(chan, 0xFF, sizeof(chan));
                cmd = DRV_IOR(ErmSpanOnDropCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
                SetErmSpanOnDropCtl(A, spanOnDropChannelEn_f, &ds, chan);
                SetErmSpanOnDropCtl(V, spanOnDropChannelId_f, &ds, MCHIP_CAP(SYS_CAP_CHANID_ILOOP));
                SetErmSpanOnDropCtl(V, spanOnDropQueueId_f, &ds, 620);
                cmd = DRV_IOW(ErmSpanOnDropCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

                sal_memset(&ds, 0, sizeof(ds));
                SetBufRetrvSpanCtl(V, spanOnDropEn_f, &ds, 1);
                SetBufRetrvSpanCtl(V, spanOnDropNextHopPtr_f, &ds, port_assign.inter_port);
                SetBufRetrvSpanCtl(V, spanOnDropRsvQueId_f, &ds, 620);
                cmd = DRV_IOW(BufRetrvSpanCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            }
            sys_usw_flow_stats_32k_ram_init(lchip);
            p_usw_register_master[lchip]->flow_record_en = 1;
            SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MASTER, 1);
        }
        break;
    case CTC_GLOBAL_MEM_CHK:
        {
            if(SDK_WORK_PLATFORM == 0)
            {
                ctc_global_mem_chk_t* p_mem_check = (ctc_global_mem_chk_t*)value;
                if (drv_ser_mem_check(lchip, p_mem_check->mem_id, p_mem_check->recover_en, &p_mem_check->chk_fail))
                {
                    return CTC_E_HW_FAIL;
                }
            }
            else
            {
                return CTC_E_NOT_SUPPORT;
            }
            break;
        }
    case CTC_GLOBAL_L2_RMAC_MATCH_EN:
        if (DRV_FROM_TMM(lchip))
        {
            IpePreLookupCtl_m ipe_pre_lkup;
            sal_memset(&ipe_pre_lkup, 0, sizeof(ipe_pre_lkup));

            /* enable router mac based on l2 lkup result */
            cmd = DRV_IOR(IpePreLookupCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_pre_lkup));

            field_val = *(bool *)value ? 1 : 0;
            SetIpePreLookupCtl(V, routerMacBasedL2Result_f, &ipe_pre_lkup, field_val);
            SetIpePreLookupCtl(V, bridePacketMode_f, &ipe_pre_lkup, field_val);         /* must config bridePacketMode else will go l2 process even if l3 lkup hit */
            SetIpePreLookupCtl(V, bridePacketModeForHash_f, &ipe_pre_lkup, field_val);  /* if bridePacketMode enable, bridePacketModeForHash must enable else vpls packet hash is not correct */
            SetIpePreLookupCtl(V, bridePacketModeForHash0_f, &ipe_pre_lkup, field_val);

            cmd = DRV_IOW(IpePreLookupCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_pre_lkup));


            /* enable router mac based on l2 lkup result */
            cmd = DRV_IOW(IpeRouteCtl_t, IpeRouteCtl_routerMacBasedL2En_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

            /* enable ip lkup and mac lkup at the same time */
            cmd = DRV_IOW(IpeLookupCtl_t, IpeLookupCtl_IpUcastMacLookup_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

            cmd = DRV_IOW(FibEngineLookupCtl_t, FibEngineLookupCtl_ipUcastMacLookupEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        break;
     case CTC_GLOBAL_WARMBOOT_INTERVAL:
        {
            uint8 enable = (*(uint32 *)value) ? 1 : 0 ;
            p_usw_register_master[lchip]->wb_interval = *(uint32 *)value;
            sys_usw_register_wb_sync_timer_en(lchip,enable);
            break;
        }
    case CTC_GLOBAL_FDB_SEARCH_DEPTH:
        {
            field_val = *(uint32*)value ? 1:0;
            cmd = DRV_FROM_AT(lchip) ? DRV_IOW(IpeLearningCtl_t, IpeLearningCtl_learningPktConflictExceptionEn_f) \
                : DRV_IOW(IpeLearningCtl_t, IpeLearningCtl_conflictExceptionEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            CTC_ERROR_RETURN(sys_usw_l2_fdb_set_search_depth(lchip, *(uint32*)value));
        }
        break;
    case CTC_GLOBAL_XPIPE_MODE:
        {
            if (!DRV_IS_TSINGMA(lchip))
            {
                return CTC_E_NOT_SUPPORT;
            }
            CTC_MAX_VALUE_CHECK(*(uint32*)value, CTC_XPIPE_MODE_2);
            cmd = DRV_IOR(QWriteGuaranteeCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

            if (!*(uint32*)value)
            {
                SetQWriteGuaranteeCtl(V, glbGuaranteeEn_f, ds, 0);
            }
            else
            {
                SetQWriteGuaranteeCtl(V, glbGuaranteeEn_f, ds, 1);
                SetQWriteGuaranteeCtl(V, mode_f, ds, (*(uint32*)value == 1) ? 0 : 1);
                if (*(uint32*)value == 2)
                {
                    uint32 srcGuaranteeEn[3];
                    sal_memset(&srcGuaranteeEn[0], 0xFF, 3*sizeof(uint32));
                    SetQWriteGuaranteeCtl(A, srcGuaranteeEn_f, ds, srcGuaranteeEn);
                }
            }
            cmd = DRV_IOW(QWriteGuaranteeCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        }
        break;
    case CTC_GLOBAL_XPIPE_ACTION:
        CTC_ERROR_RETURN(_sys_usw_global_set_xpipe_action(lchip, value));
        break;
    case CTC_GLOBAL_XPIPE_CLASSIFY:
        CTC_ERROR_RETURN(sys_usw_global_set_xpipe_classify(lchip, value));
        break;
    case CTC_GLOBAL_SID_EDIT_MODE:
        {
            field_val = *((uint32*)value)? 0 : 1;
            cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_sr6ReducedMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            p_usw_register_master[lchip]->sid_edit_mode = field_val;
        }
        break;
    case CTC_GLOBAL_FORCE_STK_PARSER:
        field_val = (*(bool*)value)? 1:0;
        cmd = DRV_IOW(IpeHeaderAdjustCtl_t, IpeHeaderAdjustCtl_forceSkipHeaderParser_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        break;
    case CTC_GLOBAL_MAX_HECMP_MEM:
        CTC_ERROR_RETURN(sys_usw_nh_set_max_hecmp(lchip, *((uint32*)value)));
        break;
    case CTC_GLOBAL_LB_HASH_GLOBAL_PROPERTY:
        CTC_ERROR_RETURN(_sys_usw_global_lb_hash_set_property(lchip, value));
        break;
    case CTC_GLOBAL_MAC_LIMIT_MODE:
        CTC_ERROR_RETURN(sys_usw_mac_limit_set_mode(lchip, (*(uint32*)value)?1:0));
        break;
    case CTC_GLOBAL_DISCARD_IP_MARTIAN_ADDR_PKT:
        CTC_ERROR_RETURN(_sys_usw_global_set_martian_address(lchip, (ctc_global_martian_addr_t *)value));
        break;
    case CTC_GLOBAL_MAX_IPV4_ICMP_PKT_SIZE:
        field_val = (*(uint32*)value);
        CTC_MAX_VALUE_CHECK(field_val, 16383);
        cmd = DRV_IOR(IpeIntfMapperCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetIpeIntfMapperCtl(V, maxIpv4IcmpLength_f, ds, field_val);
        SetIpeIntfMapperCtl(V, maxIcmpLength_f, ds, field_val);
        field_val = (field_val?1:0);
        SetIpeIntfMapperCtl(V, maxIpv4IcmpLengthEn_f, ds, field_val);
        SetIpeIntfMapperCtl(V, maxIcmpLengthEn_f, ds, field_val);
        cmd = DRV_IOW(IpeIntfMapperCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        break;
    case CTC_GLOBAL_MAX_IPV6_ICMP_PKT_SIZE:
        field_val = (*(uint32*)value);
        CTC_MAX_VALUE_CHECK(field_val, 16383);
        cmd = DRV_IOR(IpeIntfMapperCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetIpeIntfMapperCtl(V, maxIpv6IcmpLength_f, ds, field_val);
        SetIpeIntfMapperCtl(V, maxIcmpLength_f, ds, field_val);
        field_val = (field_val?1:0);
        SetIpeIntfMapperCtl(V, maxIpv6IcmpLengthEn_f, ds, field_val);
        SetIpeIntfMapperCtl(V, maxIcmpLengthEn_f, ds, field_val);
        cmd = DRV_IOW(IpeIntfMapperCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        break;
    case CTC_GLOBAL_MIN_TCP_HDR_SIZE:
        field_val = (*(uint32*)value);
        CTC_MAX_VALUE_CHECK(field_val, 63);
        cmd = DRV_IOR(ParserLayer4AppCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetParserLayer4AppCtl(V, tcpMinLength_f, ds, field_val);
        SetParserLayer4AppCtl(V, tcpMinLenMode_f, ds, field_val?1:0);
        if (field_val)
        {
            field_val = GetParserLayer4AppCtl(V, layer4ParserLengthErrorIgnore_f, ds);
            field_val &= 0xfffd;
            SetParserLayer4AppCtl(V, layer4ParserLengthErrorIgnore_f, ds, field_val);
        }
        else
        {
            field_val = GetParserLayer4AppCtl(V, layer4ParserLengthErrorIgnore_f, ds);
            field_val |= 0x0002;
            SetParserLayer4AppCtl(V, layer4ParserLengthErrorIgnore_f, ds, field_val);
        }
        cmd = DRV_IOW(ParserLayer4AppCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        break;
    case CTC_GLOBAL_DISCARD_TCP_FRAG_OFFSET_1_PKT:
        field_val = (*(bool*)value);
        cmd = DRV_IOR(ParserLayer4AppCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        field_val = field_val?(GetParserLayer4AppCtl(V, tcpFragCheck_f, ds)|0x2):(GetParserLayer4AppCtl(V, tcpFragCheck_f, ds)&0x5);
        SetParserLayer4AppCtl(V, tcpFragCheck_f, ds, field_val);
        cmd = DRV_IOW(ParserLayer4AppCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        break;
    #if defined E_UNIT && (FEATURE_MODE == 0)
    case CTC_GLOBAL_NPM_IM_COLOR_HW_EN:
        if (DRV_FROM_AT(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        field_val = (*(uint32*)value)?1:0;
        CTC_ERROR_RETURN(SYS_CB_RET(CTC_E_NOT_INIT, SYS_CB_NPM_IM_SET_ECPU_EN,lchip,field_val));
        break;
    #endif
    case CTC_GLOBAL_SCL_PAYLOAD_OFFSET_GRANU:
        if(DRV_FROM_TMM(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        CTC_MAX_VALUE_CHECK(*(uint32*)value, CTC_SCL_PAYLOAD_OFFSET_GRANU_MAX - 1);
        field_val = (*(uint32*)value);
        cmd = DRV_IOR(IpeSclFlowCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        SetIpeSclFlowCtl(V, removeByteShift_f, ds, field_val);
        cmd = DRV_IOW(IpeSclFlowCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        break;
     case CTC_GLOBAL_ECO_EN:
        CTC_MAX_VALUE_CHECK(*(uint32*)value, CTC_GLOBAL_ECO_MAX - 1);
        if (1 == SDK_WORK_PLATFORM)
        {
            return CTC_E_NOT_SUPPORT;
        }
        val = (*(uint32*)value);
        if(DRV_FROM_AT(lchip))
        {
            if (CTC_FLAG_ISSET(val, CTC_GLOBAL_ECO_OOBFC))
            {
                return CTC_E_NOT_SUPPORT;
            }
            cmd = DRV_IOR(CtcBufStoreProcTopCtlModuleEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            field_val = CTC_FLAG_ISSET(val, CTC_GLOBAL_ECO_MDIO) ? 0 : 1;
            SetCtcBufStoreProcTopCtlModuleEnable(V, enClkMdio0_f, ds, field_val);
            SetCtcBufStoreProcTopCtlModuleEnable(V, enClkMdio1_f, ds, field_val);

            field_val = CTC_FLAG_ISSET(val, CTC_GLOBAL_ECO_LED) ? 0 : 1;
            SetCtcBufStoreProcTopCtlModuleEnable(V, enClkLed_f, ds, field_val);

            cmd = DRV_IOW(CtcBufStoreProcTopCtlModuleEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

            cmd = DRV_IOR(CtcMiscCtlModuleEn_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

            field_val = CTC_FLAG_ISSET(val, CTC_GLOBAL_ECO_MCU) ? 0 : 1;
            SetCtcMiscCtlModuleEn(V, enClkMcu_f, ds, field_val);
            SetCtcMiscCtlModuleEn(V, enClkMcuIntf_f, ds, field_val);

            cmd = DRV_IOW(CtcMiscCtlModuleEn_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

            field_val = CTC_FLAG_ISSET(val, CTC_GLOBAL_ECO_GPIO) ? 0 : 1;
            cmd = DRV_IOR(GpioEnClk_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            SetGpioEnClk(V, cfgGpioEnClk_f, ds, field_val);
            cmd = DRV_IOW(GpioEnClk_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

            field_val = CTC_FLAG_ISSET(val, CTC_GLOBAL_ECO_I2C) ? 0 : 1;
            cmd = DRV_IOR(SupEnClk_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            SetSupEnClk(V, cfgEnClkI2CMaster0_f, ds, field_val);
            SetSupEnClk(V, cfgEnClkI2CMaster1_f, ds, field_val);
            cmd = DRV_IOW(SupEnClk_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        }
        else
        {
            cmd = DRV_IOR(CtcMiscCtlClkEn_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            field_val = CTC_FLAG_ISSET(val, CTC_GLOBAL_ECO_MDIO) ? 0 : 1;
            SetCtcMiscCtlClkEn(V, enClkMdio0_f, ds, field_val);
            SetCtcMiscCtlClkEn(V, enClkMdio1_f, ds, field_val);

            field_val = CTC_FLAG_ISSET(val, CTC_GLOBAL_ECO_OOBFC) ? 0 : 1;
            SetCtcMiscCtlClkEn(V, enClkOobFc_f, ds, field_val);

            field_val = CTC_FLAG_ISSET(val, CTC_GLOBAL_ECO_LED) ? 0 : 1;
            SetCtcMiscCtlClkEn(V, enClkLed0_f, ds, field_val);
            SetCtcMiscCtlClkEn(V, enClkLed1_f, ds, field_val);

            field_val = CTC_FLAG_ISSET(val, CTC_GLOBAL_ECO_MCU) ? 0 : 1;
            SetCtcMiscCtlClkEn(V, enClkMcu_f, ds, field_val);
            SetCtcMiscCtlClkEn(V, enClkMcuIntf_f, ds, field_val);

            cmd = DRV_IOW(CtcMiscCtlClkEn_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        }

        /* eco hibernate enable, must firset config val==0, and use hw-reset en to restore all*/
        field_val = CTC_FLAG_ISSET(val, CTC_GLOBAL_ECO_HIBERNATE)?1:0;
        if ((1 == field_val) || (0 == val))
        {
            CTC_ERROR_RETURN(_sys_usw_global_set_eco_hibernate_en(lchip, field_val));
        }
        break;
    case CTC_GLOBAL_TRUNCATION_LEN_PROFILE:
        {
            uint8  shift_hw = 0;
            uint8  len_hw = 0;
            DsTruncationProfile_m truncation_prof;
            ctc_truncation_len_t* p_truncation_len = (ctc_truncation_len_t*)value;

            CTC_VALUE_RANGE_CHECK(p_truncation_len->profile_id, SYS_TRUNCATION_PROFILE_USER_START, SYS_TRUNCATION_PROFILE_USER_END);
            CTC_MAX_VALUE_CHECK(p_truncation_len->truncated_len, MCHIP_CAP(SYS_CAP_PKT_TRUNCATED_LEN));

            CTC_ERROR_RETURN(_sys_usw_map_truncation_len_user_to_hw(p_truncation_len->truncated_len, &len_hw, &shift_hw));
            cmd = DRV_IOR(DsTruncationProfile_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, p_truncation_len->profile_id, cmd, &truncation_prof));
            SetDsTruncationProfile(V, lengthShift_f, &truncation_prof, shift_hw);
            SetDsTruncationProfile(V, length_f, &truncation_prof, len_hw);
            cmd = DRV_IOW(DsTruncationProfile_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, p_truncation_len->profile_id, cmd, &truncation_prof));
        }
        break;
    case CTC_GLOBAL_TRUNCATION_LEN:
        {
            field_val = (*(uint32*)value);
            CTC_MAX_VALUE_CHECK(field_val, MCHIP_CAP(SYS_CAP_PKT_TRUNCATED_LEN));
            cmd = DRV_IOR(EpeHeaderEditTruncationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &truncationctl));
            SetEpeHeaderEditTruncationCtl(V, cfgTruncationLen_f, &truncationctl, field_val);
            cmd = DRV_IOW(EpeHeaderEditTruncationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &truncationctl));
        }
        break;
    case CTC_GLOBAL_TRUNCATION_MODE:
        {
            uint8 mode;
            field_val = (*(uint32*)value);
            CTC_MAX_VALUE_CHECK(field_val, CTC_TRUNCATION_MODE_2);
            switch(field_val)
            {
                case CTC_TRUNCATION_MODE_1:
                    mode = 1;
                    break;
                case CTC_TRUNCATION_MODE_2:
                    mode = 3;
                    break;
                default:
                    mode = field_val;
                    break;
            }
            cmd = DRV_IOR(EpeHeaderEditTruncationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &truncationctl));
            SetEpeHeaderEditTruncationCtl(V, cfgTruncationMode_f, &truncationctl, mode);
            cmd = DRV_IOW(EpeHeaderEditTruncationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &truncationctl));
        }
        break;
    case CTC_GLOBAL_MACDA_HIT_AGING_EN:
        {
            FibEngineLookupResultCtl_m lookupResultCtl;
            uint32 ctl_bmp = 0;
            field_val = (*(uint32 *)value) ? 1 : 0 ;
            /*((macDa(40) && (!FibEngineLookupResultCtl.daAgingControlBit(1))) || ((!FibInputKey.macDa(40)) && (!FibEngineLookupResultCtl.daAgingControlBit(0))))*/
            ctl_bmp = (*(uint32 *)value) == 2 ? 0x1 : ((*(uint32 *)value) == 3 ? 0x02 : 0);
            cmd = DRV_IOR(FibEngineLookupResultCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lookupResultCtl));
            SetFibEngineLookupResultCtl(V, gMacDaLookupResultCtl_agingEn_f, &lookupResultCtl, field_val);
            SetFibEngineLookupResultCtl(V, daAgingControlBit_f, &lookupResultCtl, ctl_bmp);   /* bit 0 for uc, bit 1 for mc ,value 0 means aging en*/
            cmd = DRV_IOW(FibEngineLookupResultCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lookupResultCtl));
        }
        break;
    case CTC_GLOBAL_LOOP_MODE:
        {
            uint8 mode = 0;
            if (((SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_A) && DRV_IS_TMM(lchip)) || DRV_IS_TMG(lchip))
            {
                return CTC_E_NOT_SUPPORT;
            }
            field_val = (*(uint32*)value);
            CTC_MAX_VALUE_CHECK(field_val, 2);
            CTC_ERROR_RETURN(sys_usw_internal_port_get_loop_mode(lchip, &mode));
            if (field_val == mode)
            {
                return CTC_E_NONE;
            }
            if (1 == mode)
            {
                sys_usw_linkagg_loop_chan_lag_en(lchip, FALSE);
            }
            else if (2 == mode)
            {
                sys_usw_internal_port_eloop_port(lchip, FALSE);
            }

            if (1 == field_val)
            {
                sys_usw_linkagg_loop_chan_lag_en(lchip, TRUE);
            }
            else if (2 == field_val)
            {
                sys_usw_internal_port_eloop_port(lchip, TRUE);
            }
        }
        break;
    case CTC_GLOBAL_DECAPED_FORCE_IPMC:
        {
            IpePreLookupCtl_m ipe_pre_lkup;
            cmd = DRV_IOR(IpePreLookupCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_pre_lkup));

            field_val = *(uint32*)value ? 1 : 0;
            SetIpePreLookupCtl(V, routeAfterDecapMcastEn_f, &ipe_pre_lkup, field_val);

            cmd = DRV_IOW(IpePreLookupCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_pre_lkup));
        }
        break;
    case CTC_GLOBAL_MCAST_LOGIC_REP_THRD:
        if (!DRV_FROM_TMM(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }

        if (*(uint32 *)value < SYS_USW_REGISTER_MIN_LOGIC_THRD || *(uint32 *)value > SYS_USW_REGISTER_MAX_LOGIC_THRD)
        {
            return CTC_E_INVALID_PARAM;
        }
        p_usw_register_master[lchip]->logic_rep_threshold = *(uint32 *)value;
        SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MASTER, 1);
        break;
    case CTC_GLOBAL_STATION_MOVE_MODE:
    {
        ds_t ds;
        field_val = *(uint32*)value ? 1 : 0;
        p_usw_register_master[lchip]->station_move_mode = field_val;
        SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_REGISTER, SYS_WB_APPID_REGISTER_SUBID_MASTER, 1);
        cmd = DRV_IOR(IpeIntfMapperXCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetIpeIntfMapperXCtl(V, cidMask_f, &ds, (field_val? 0xF000 : 0));
        cmd = DRV_IOW(IpeIntfMapperXCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    }
        break;
    default:
        return CTC_E_NOT_SUPPORT;
    }

    return CTC_E_NONE;
}

int32
sys_usw_global_ctl_get(uint8 lchip, ctc_global_control_type_t type, void* value)
{
    uint32 field_val = 0;
    uint8 enable = 0;
    uint32 cmd = 0;
    uint32 base_table = 0;
    ds1_t ds;
    ctc_global_overlay_decap_mode_t* p_decap_mode = (ctc_global_overlay_decap_mode_t*)value;
    HmacEngineCtl_m hmac_engine_ctl;
    EpeHeaderEditTruncationCtl_m truncationctl;
    ctc_global_hmac_t* p_hmac = NULL;

    SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    CTC_PTR_VALID_CHECK(value);
    SYS_REGISTER_INIT_CHECK;

    switch(type)
    {
    case CTC_GLOBAL_LOGIC_PORT_ISOLATE_EN:
        cmd = DRV_IOR(EpeNextHopCtl_t, EpeNextHopCtl_supportLogicPortIsolation_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, (uint32*)value));
        break;
    case CTC_GLOBAL_VCHIP_INFO:
        ((ctc_global_vchip_info_t*)value)->pp_base = drv_vchip_get_pp_base(lchip);
        ((ctc_global_vchip_info_t*)value)->pp_num = drv_vchip_get_pp_num(lchip);
        break;
    case CTC_GLOBAL_NPM_IM_EN:   /* TMM: support Mpls IM */
        cmd = DRV_IOR(EpePktProcCtl_t, EpePktProcCtl_ecnIgnoreCheck_f);
        DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val);
        if (field_val)
        {
            CTC_SET_FLAG(*(uint32 *)value, CTC_GLOBAL_NPM_IM_IP_ECN);
        }
        if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
        {
            cmd = DRV_IOR(ParserMplsCtl_t, ParserMplsCtl_supportMplsInbandOam_f);
            DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val);
            if (field_val)
            {
                CTC_SET_FLAG(*(uint32 *)value, CTC_GLOBAL_NPM_IM_MPLS);
            }
        }
        break;
    case CTC_GLOBAL_NPM_IM_LOSS_PROF_INTERVAL:
        if (DRV_FROM_AT(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        CTC_ERROR_RETURN(SYS_CB(SYS_CB_NPM_IM_GET_LOSS_PROFILE, lchip, (void*)value));
        break;
    case CTC_GLOBAL_ESLB_EN:   /* TMM: support MplsEvpn */
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(IpeMplsCtl_t, IpeMplsCtl_supportMplsEvpn_f);
            DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val);
            *(uint32 *)value = field_val? TRUE: FALSE;
        }
        else if ((SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) && DRV_IS_TSINGMA(lchip))
        {
            cmd = DRV_IOR(IpeIntfMapReserved_t, IpeIntfMapReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            if (CTC_IS_BIT_SET(field_val, 1))
            {
                *(uint32*)value = 1;
            }
            else
            {
                *(uint32*)value = 0;
            }
        }
        else
        {
            return CTC_E_NOT_SUPPORT;
        }
        break;
    case CTC_GLOBAL_HMAC_EN:
        if(!MCHIP_SUB_FEATURE_CAP(lchip, SYS_FEATURE_HMAC))
        {
            return CTC_E_NOT_SUPPORT;
        }
        p_hmac = value;
        cmd = DRV_IOR(HmacEngineCtl_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, cmd, &hmac_engine_ctl);
        p_hmac->enable = GetHmacEngineCtl(V, hmacEn_f, &hmac_engine_ctl);
        p_hmac->ip_protocol_en = GetHmacEngineCtl(V, ipProtocolReplaceEn_f, &hmac_engine_ctl);
        p_hmac->ip_protocol = GetHmacEngineCtl(V, ipProtocolReplaceValue_f, &hmac_engine_ctl);
        GetHmacEngineCtl(A, ipHeaderMask_f, &hmac_engine_ctl, p_hmac->ip_header_mask);
        SYS_USW_HMAC_SET_IP_HEADER_HW(p_hmac->ip_header_mask, CTC_IP_HEADER_LEN);
        break;
    case CTC_GLOBAL_DISCARD_SAME_MACDASA_PKT:
        cmd = DRV_IOR(IpeIntfMapperCtl_t, IpeIntfMapperCtl_discardSameMacAddr_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool *)value = field_val?TRUE:FALSE;
        break;

    case CTC_GLOBAL_DISCARD_SAME_IPDASA_PKT:
        cmd = DRV_IOR(IpeIntfMapperCtl_t, IpeIntfMapperCtl_discardSameIpAddr_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool *)value = field_val?TRUE:FALSE;
        break;

    case CTC_GLOBAL_DISCARD_TTL_0_PKT:
        cmd = DRV_IOR(EpePktProcCtl_t, EpePktProcCtl_discardMplsTagTtl0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool *)value = field_val?TRUE:FALSE;
        break;

    case CTC_GLOBAL_DISCARD_MCAST_SA_PKT:
        cmd = DRV_IOR(IpeIntfMapperCtl_t, IpeIntfMapperCtl_allowMcastMacSa_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool *)value = field_val?FALSE:TRUE;
        break;

    case CTC_GLOBAL_ACL_CHANGE_COS_ONLY:
        #if 0
        cmd = DRV_IOR(IpeAclQosCtl_t, IpeAclQosCtl_aclMergeVlanAction_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool *)value = field_val ? TRUE:FALSE;
        #endif
        break;

    case CTC_GLOBAL_ECMP_DLB_MODE:
        cmd = DRV_IOR(IpeEcmpCtl_t, IpeEcmpCtl_dlbEnableMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        if (1 == field_val)
        {
            *(uint32*)value = CTC_GLOBAL_ECMP_DLB_MODE_ELEPHANT;
        }
        else if (3 == field_val)
        {
            *(uint32*)value = CTC_GLOBAL_ECMP_DLB_MODE_TCP;
        }
        else if (2 == field_val)
        {
            *(uint32*)value = CTC_GLOBAL_ECMP_DLB_MODE_ALL;
        }
        break;

    case CTC_GLOBAL_ECMP_REBALANCE_MODE:
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(EcmpDlbEngineCtl_t, EcmpDlbEngineCtl_rebalanceMode_f);
        }
        else
        {
            cmd = DRV_IOR(DlbEngineCtl_t, DlbEngineCtl_rebalanceMode_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        if (0 == field_val)
        {
            *(uint32*)value = CTC_GLOBAL_ECMP_REBALANCE_MODE_FIRST;
        }
        else if (1 == field_val)
        {
            *(uint32*)value = CTC_GLOBAL_ECMP_REBALANCE_MODE_PACKET;
        }
        else if (2 == field_val)
        {
            *(uint32*)value = CTC_GLOBAL_ECMP_REBALANCE_MODE_NORMAL;
        }
        break;

     case CTC_GLOBAL_ECMP_FLOW_AGING_INTERVAL:
         if (DRV_FROM_TMM(lchip))
         {
             cmd = DRV_IOR(EcmpDlbEngineTimerCtl_t, EcmpDlbEngineTimerCtl_cfgRefDivAgingRstPulse_f);
         }
         else
         {
             cmd = DRV_IOR(DlbEngineTimerCtl_t, DlbEngineTimerCtl_cfgRefDivAgingRstPulse_f);
         }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(uint32*)value = field_val / 250;
        break;

    case CTC_GLOBAL_ECMP_FLOW_INACTIVE_INTERVAL:
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(EcmpDlbEngineTimerCtl_t, EcmpDlbEngineTimerCtl_cfgRefDivInactiveRstPulse_f);
        }
        else
        {
            cmd = DRV_IOR(DlbEngineTimerCtl_t, DlbEngineTimerCtl_cfgRefDivInactiveRstPulse_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(uint32*)value = field_val << 3;
        break;

    case CTC_GLOBAL_ECMP_FLOW_PKT_INTERVAL:
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(EcmpDlbEngineCtl_t, EcmpDlbEngineCtl_reorderPktIntervalMode_f);
        }
        else
        {
            cmd = DRV_IOR(DlbEngineCtl_t, DlbEngineCtl_reorderPktIntervalMode_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        if (0 == field_val)
        {
            *(uint32*)value = 1024;
        }
        else if (1 == field_val)
        {
            *(uint32*)value = 256;
        }
        else if (2 == field_val)
        {
            *(uint32*)value = 8192;
        }
        else if (3 == field_val)
        {
            *(uint32*)value = 32768;
        }
        break;
    case CTC_GLOBAL_SPM_AGING_INTERVAL:
        if (DRV_FROM_TMM(lchip))
        {
            uint64 temp = 0;
            uint32 interval = 0;
            uint32 aging_min_ptr = 0;
            uint32 aging_max_ptr = 0;
            uint32 core_frequency  = 0;

            if(DRV_FROM_AT(lchip))
            {
                PpAgingCtl_m pp_aging_ctl;
                PpAgingScanRangeCtl_m pp_scan_ctl;

                cmd = DRV_IOR(PpAgingCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pp_aging_ctl));

                cmd = DRV_IOR(PpAgingScanRangeCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pp_scan_ctl));

                field_val = GetPpAgingCtl(V, gTimmer_1_agingEn_f, &pp_aging_ctl);
                interval = GetPpAgingCtl(V, gTimmer_1_agingInterval_f, &pp_aging_ctl);
                aging_min_ptr = GetPpAgingScanRangeCtl(V, gTimmer_1_minPtr_f, &pp_scan_ctl);
                aging_max_ptr = GetPpAgingScanRangeCtl(V, gTimmer_1_maxPtr_f, &pp_scan_ctl);
            }
            else
            {
                IpeAgingCtl_m ipe_aging_ctl;
                IpeAgingScanRangeCtl_m ipe_scan_ctl;

                cmd = DRV_IOR(IpeAgingCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_aging_ctl));

                cmd = DRV_IOR(IpeAgingScanRangeCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_scan_ctl));

                field_val = GetIpeAgingCtl(V, gTimmer_1_agingEn_f, &ipe_aging_ctl);
                interval = GetIpeAgingCtl(V, gTimmer_1_agingInterval_f, &ipe_aging_ctl);
                aging_min_ptr = GetIpeAgingScanRangeCtl(V, gTimmer_1_minPtr_f, &ipe_scan_ctl);
                aging_max_ptr = GetIpeAgingScanRangeCtl(V, gTimmer_1_maxPtr_f, &ipe_scan_ctl);
            }

            if (field_val)
            {

                core_frequency = sys_usw_get_core_freq(lchip, 0) * 1000000 / DOWN_FRE_RATE;
                temp = (uint64)(interval + 1)*(aging_max_ptr - aging_min_ptr);
                *(uint32*)value = (temp - 1) / core_frequency;
            }
            else
            {
                /* not enable */
                *(uint32*)value = 0;
            }
        }
        break;

    case CTC_GLOBAL_LINKAGG_FLOW_INACTIVE_INTERVAL:
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(LagEngineTimerCtl_t, LagEngineTimerCtl_tsThreshold_f);
        }
        else
        {
            cmd = DRV_IOR(LagEngineTimerCtl0_t, LagEngineTimerCtl0_tsThreshold0_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(uint32*)value = field_val;
        break;
    case CTC_GLOBAL_STACKING_TRUNK_FLOW_INACTIVE_INTERVAL:
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(LagEngineTimerCtl_t, LagEngineTimerCtl_tsThreshold_f);
        }
        else
        {
            cmd = DRV_IOR(LagEngineTimerCtl1_t, LagEngineTimerCtl1_tsThreshold1_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(uint32*)value = field_val;
        break;
    case CTC_GLOBAL_LAG_DLB_PROPERTY:
        if ((NULL == MCHIP_LAG(lchip)) || (NULL == MCHIP_LAG(lchip)->dlb_get_cfg))
        {
            return CTC_E_NOT_SUPPORT;
        }
        CTC_ERROR_RETURN(MCHIP_LAG(lchip)->dlb_get_cfg(lchip, value));
        break;
    case CTC_GLOBAL_DISCARD_TCP_SYN_0_PKT:
        cmd = DRV_IOR(ParserLayer4AppCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        field_val = GetParserLayer4AppCtl(V, tcpFragCheck_f, ds) & 0x4;
        (*(bool*)value) = field_val?TRUE:FALSE;
        break;
    case CTC_GLOBAL_DISCARD_TCP_NULL_PKT:
    case CTC_GLOBAL_DISCARD_TCP_XMAS_PKT:
    case CTC_GLOBAL_DISCARD_TCP_SYN_FIN_PKT:
    case CTC_GLOBAL_DISCARD_SAME_L4_PORT_PKT:
    case CTC_GLOBAL_DISCARD_ICMP_FRAG_PKT:
        CTC_ERROR_RETURN(_sys_usw_global_ctl_l4_check_en(lchip, type, ((bool*)value), 0));
        break;

    case CTC_GLOBAL_ARP_MACDA_CHECK_EN:
    case CTC_GLOBAL_ARP_MACSA_CHECK_EN:
    case CTC_GLOBAL_ARP_IP_CHECK_EN:
    case CTC_GLOBAL_ARP_CHECK_FAIL_TO_CPU:
    case CTC_GLOBAL_GRATUITOUS_ARP_TO_CPU:
    case CTC_GLOBAL_ARP_LOCAL_CHECK_EN:
        CTC_ERROR_RETURN(_sys_usw_global_ctl_get_arp_check_en(lchip, type, ((uint32*)&field_val)));
        *(bool*)value = field_val ? TRUE : FALSE;
        break;
    case CTC_GLOBAL_IGMP_SNOOPING_MODE:
        CTC_ERROR_RETURN(_sys_usw_global_ctl_get_igmp_mode(lchip, type, ((uint32*)value)));
        break;
    case CTC_GLOBAL_CHIP_CAPABILITY:
        CTC_ERROR_RETURN(_sys_usw_global_get_chip_capability(lchip, (uint32*)value));
        break;

    case CTC_GLOBAL_FLOW_PROPERTY:
        CTC_ERROR_RETURN(_sys_usw_get_glb_flow_property(lchip, (ctc_global_flow_property_t*)value));
        break;

    case CTC_GLOBAL_ACL_LKUP_PROPERTY:
        CTC_ERROR_RETURN(_sys_usw_get_glb_acl_lkup_property(lchip, (ctc_acl_property_t*)value));
        break;
    case CTC_GLOBAL_ACL_PROPERTY:
        CTC_ERROR_RETURN(sys_usw_get_glb_acl_property(lchip, (ctc_global_acl_property_t*)value, 0));
        break;
    case CTC_GLOBAL_SCL_PROPERTY:
        CTC_ERROR_RETURN(_sys_usw_get_glb_scl_property(lchip, (ctc_global_scl_property_t*)value));
        break;
    case CTC_GLOBAL_PIM_SNOOPING_MODE:
        cmd = DRV_IOR(IpeLookupCtl_t, IpeLookupCtl_pimSnoopingEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(uint32 *)value = field_val ? 0 : 1;
        break;
    case CTC_GLOBAL_IPMC_PROPERTY:
        CTC_ERROR_RETURN(_sys_usw_get_glb_ipmc_property(lchip, (ctc_global_ipmc_property_t*)value));
        break;
    case CTC_GLOBAL_CID_PROPERTY:
        CTC_ERROR_RETURN(_sys_usw_get_glb_cid_property(lchip, (ctc_global_cid_property_t*)value));
         break;

    case CTC_GLOBAL_VXLAN_UDP_DEST_PORT:
        cmd = DRV_IOR(ParserLayer4AppCtl_t, ParserLayer4AppCtl_vxlanUdpDestPort_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(uint32*)value = field_val;
        break;
    case CTC_GLOBAL_GENEVE_UDP_DEST_PORT:
        cmd = DRV_IOR(ParserLayer4AppCtl_t, ParserLayer4AppCtl_geneveVxlanUdpDestPort_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(uint32*)value = field_val;
		break;
    case CTC_GLOBAL_WARMBOOT_CPU_RX_EN:
        if (p_usw_register_master[lchip]->wb_keep_knet==1)
        {
            *(uint32 *)value = 2;
        }
        else
        {
            CTC_ERROR_RETURN(sys_usw_interrupt_get_group_en(lchip, &enable));
            *(uint32 *)value = (!enable)?0:1;
        }
        break;
    case CTC_GLOBAL_ELOOP_USE_LOGIC_DESTPORT:
        cmd = DRV_IOR(EpeHeaderEditCtl_t, EpeHeaderEditCtl_ingressEditUseLogicPortSelect_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool *)value = (field_val)?TRUE:FALSE;
        break;
    case CTC_GLOBAL_NH_FORCE_BRIDGE_DISABLE:
        cmd = DRV_IOR(EpeNextHopCtl_t, EpeNextHopCtl_forceBridgeL3Match_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool *)value = (field_val)?FALSE:TRUE;
        break;

    case CTC_GLOBAL_NH_MCAST_LOGIC_REP_EN:
        *(bool *)value = sys_usw_nh_is_ipmc_logic_rep_enable(lchip);
        break;

	case CTC_GLOBAL_LB_HASH_KEY:
        if ((NULL == MCHIP_HASH(lchip)) || (NULL == MCHIP_HASH(lchip)->get_cfg))
        {
            return CTC_E_NOT_SUPPORT;
        }
        CTC_ERROR_RETURN(MCHIP_HASH(lchip)->get_cfg(lchip, value));

        break;
    case CTC_GLOBAL_LB_HASH_OFFSET_PROFILE:
        if ((NULL == MCHIP_HASH(lchip)) || (NULL == MCHIP_HASH(lchip)->get_offset))
        {
            return CTC_E_NOT_SUPPORT;
        }
        CTC_ERROR_RETURN(MCHIP_HASH(lchip)->get_offset(lchip, value));
        break;
    case CTC_GLOBAL_OAM_POLICER_EN:
        if (DRV_IS_DUET2(lchip))
        {
            cmd = DRV_IOR(IpeFwdCtl_t, IpeFwdCtl_oamBypassPolicingOp_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        else
        {
            cmd = DRV_IOR(IpeAclQosCtl_t, IpeAclQosCtl_oamBypassPolicingOp_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        *(bool *)value = (field_val)?FALSE:TRUE;
        break;
    case CTC_GLOBAL_PANEL_PORTS:
        CTC_ERROR_RETURN(_sys_usw_global_get_panel_ports(lchip, (ctc_global_panel_ports_t*)value));
        break;
	case CTC_GLOBAL_PARSER_OUTER_ALWAYS_CVLAN_EN:
        cmd = DRV_IOR(ParserEthernetCtl_t, ParserEthernetCtl_outerAlwaysCvlan_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool *)value = (field_val)? TRUE : FALSE;
        break;
    case CTC_GLOBAL_VPWS_SNOOPING_PARSER:
        cmd = DRV_IOR(IpeTunnelIdCtl_t, IpeTunnelIdCtl_vpwsDecapsForceSecondParser_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool *)value = (field_val) ? TRUE : FALSE;
        break;

    case CTC_GLOBAL_ARP_VLAN_CLASS_EN:
        cmd = DRV_FROM_TMM(lchip)? DRV_IOR(UserIdCtl_t, UserIdCtl_arpForceIpv4_f): DRV_IOR(IpeUserIdCtl_t, IpeUserIdCtl_arpForceIpv4_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool*)value = field_val;
        break;
    case CTC_GLOBAL_NH_ARP_MACDA_DERIVE_MODE:
        *(uint32 *)value = p_usw_register_master[lchip]->derive_mode;
        break;
    case CTC_GLOBAL_VXLAN_CRYPT_UDP_DEST_PORT:
        if (DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOR(XSecTxEncryptDpCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_DP_EN(cmd, 0), &ds));
            field_val = GetXSecTxEncryptDpCtl(V, ctcSecUdpPort_f, &ds);
        }
        else if((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
        {
            cmd = DRV_IOR(IpeUserIdCtl_t, IpeUserIdCtl_cloudSecUdpPort_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        else
        {
            cmd = DRV_IOR(ParserLayer4AppCtl_t, ParserLayer4AppCtl_encryptVxlanUdpDestPort_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        *(uint32 *)value =field_val;
        break;
    case CTC_GLOBAL_DOT1AE_CRYPT_CTCSH_UDP_DEST_PORT:
        cmd = DRV_IOR(XSecTxEncryptDpCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_DP_EN(cmd, 0), &ds));
        field_val = GetXSecTxEncryptDpCtl(V, ctcSecShimUdpPort_f, &ds);
        *(uint32 *)value =field_val;
        break;
    case CTC_GLOBAL_DOT1AE_CRYPT_IP_PROTOCOL:
        cmd = DRV_IOR(XSecRxParserDpCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_DP_EN(cmd, 0), &ds));
        field_val = GetXSecRxParserDpCtl(V, ipCtcSecProtocol_f, &ds);
        *(uint32 *)value =field_val;
        break;
    case CTC_GLOBAL_DOT1AE_CRYPT_CTCSH_IP_PROTOCOL:
        cmd = DRV_IOR(XSecRxParserDpCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_DP_EN(cmd, 0), &ds));
        field_val = GetXSecRxParserDpCtl(V, ipCtcSecShimProtocol_f, &ds);
        *(uint32 *)value = field_val;
		break;
    case CTC_GLOBAL_DISCARD_MACSA_0_PKT:
        cmd = DRV_IOR(IpeIntfMapperCtl_t, IpeIntfMapperCtl_discardAllZeroMacSa_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool*)value = field_val;
        break;
    case CTC_GLOBAL_TPOAM_VPWSOAM_COEXIST:
        if (!DRV_IS_DUET2(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        *(uint32 *)value = p_usw_register_master[lchip]->tpoam_vpws_coexist ? 1 : 0;
        break;
    case CTC_GLOBAL_VXLAN_POLICER_GROUP_ID_BASE:
        if (DRV_FROM_TMM(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(EpePktProcCtl_t, EpePktProcCtl_vxlanPolicyGidBase_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(uint32 *)value =field_val;
        break;
    case CTC_GLOBAL_IGS_RANDOM_LOG_SHIFT:
        cmd = DRV_IOR(IpeUserIdCtl_t, IpeUserIdCtl_randomLogShift_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(uint32*)value = field_val;
        break;
    case CTC_GLOBAL_EGS_RANDOM_LOG_SHIFT:
        cmd = DRV_IOR(EpeNextHopCtl_t, EpeNextHopCtl_randomLogShift_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(uint32*)value = field_val;
        break;
    case CTC_GLOBAL_OVERLAY_DECAP_MODE:
        CTC_MAX_VALUE_CHECK(p_decap_mode->scl_id, 1);

        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(UserIdCtl_t, (p_decap_mode->scl_id)? UserIdCtl_vxlanTunnelHash1LkpMode_f: UserIdCtl_vxlanTunnelHash0LkpMode_f);
        }
        else
        {
            cmd = DRV_IOR(IpeUserIdCtl_t, DRV_IS_DUET2(lchip) ? \
                ((p_decap_mode->scl_id)? IpeUserIdCtl_vxlanTunnelHash2LkpMode_f: IpeUserIdCtl_vxlanTunnelHash1LkpMode_f):\
                ((p_decap_mode->scl_id)? IpeUserIdCtl_vxlanTunnelHash1LkpMode_f: IpeUserIdCtl_vxlanTunnelHash0LkpMode_f));
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        p_decap_mode->vxlan_mode = field_val ? 0:1;

        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(UserIdCtl_t, (p_decap_mode->scl_id)? UserIdCtl_nvgreTunnelHash1LkpMode_f: UserIdCtl_nvgreTunnelHash0LkpMode_f);
        }
        else
        {
            cmd = DRV_IOR(IpeUserIdCtl_t, DRV_IS_DUET2(lchip) ? \
                ((p_decap_mode->scl_id)? IpeUserIdCtl_nvgreTunnelHash2LkpMode_f: IpeUserIdCtl_nvgreTunnelHash1LkpMode_f):
                ((p_decap_mode->scl_id)? IpeUserIdCtl_nvgreTunnelHash1LkpMode_f: IpeUserIdCtl_nvgreTunnelHash0LkpMode_f));
        }

        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        p_decap_mode->nvgre_mode = field_val ? 0:1;

        break;

    case CTC_GLOBAL_EGS_STK_ACL_DIS:
        cmd = DRV_IOR(EpeAclQosCtl_t, EpeAclQosCtl_stackingDisableAcl_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool*)value = field_val;
        break;
   case CTC_GLOBAL_STK_WITH_IGS_PKT_HDR_EN:
        cmd = DRV_IOR(EpeHdrAdjustCtl_t, EpeHdrAdjustCtl_toRemoteCpuAttachHeader_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool*)value = field_val;
        break;
   case CTC_GLOBAL_L2_RMAC_MATCH_EN:
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(IpeRouteCtl_t, IpeRouteCtl_routerMacBasedL2En_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            *(bool *)value = field_val? TRUE : FALSE;
        }
        break;
  case CTC_GLOBAL_WARMBOOT_INTERVAL:
        *(uint32*)value = p_usw_register_master[lchip]->wb_interval;
        break;
    case CTC_GLOBAL_FDB_SEARCH_DEPTH:
        CTC_ERROR_RETURN(sys_usw_l2_fdb_get_search_depth(lchip, (uint32*)value));
        break;
    case CTC_GLOBAL_NET_RX_EN:
        if(!DRV_IS_TSINGMA(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        base_table = Sgmac0RxCfg0_t;
        cmd = DRV_IOR(base_table, Sgmac0RxCfg0_cfgSgmac0RxPktEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        (*(uint32*)value) = field_val;
        break;
    case CTC_GLOBAL_EACL_SWITCH_ID:
        if (0 == ((SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) && DRV_IS_TSINGMA(lchip)))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(EpeScheduleReserved_t, EpeScheduleReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        if (CTC_IS_BIT_SET(field_val, 0))
        {
            *(uint32*)value = (field_val>>1)&0x3FF;
        }
        else
        {
            *(uint32*)value = 0xFFFF;
        }
        break;
	case CTC_GLOBAL_XPIPE_MODE:
        {
            QWriteGuaranteeCtl_m ds;
            uint32 mode = 0;

            if (!DRV_IS_TSINGMA(lchip))
            {
                return CTC_E_NOT_SUPPORT;
            }
            cmd = DRV_IOR(QWriteGuaranteeCtl_t, DRV_ENTRY_FLAG);
            DRV_IOCTL(lchip, 0, cmd, &ds);
            *(uint32*)value = GetQWriteGuaranteeCtl(V, glbGuaranteeEn_f, &ds);
            if (!*(uint32*)value)
            {
                return CTC_E_NONE;
            }
            else
            {
                mode = GetQWriteGuaranteeCtl(V, mode_f, &ds);
                *(uint32*)value = (mode == 0) ? 1 : 2;
            }
        }
        break;
     case CTC_GLOBAL_XPIPE_ACTION:
        CTC_ERROR_RETURN(_sys_usw_global_get_xpipe_action(lchip, value));
        break;
     case CTC_GLOBAL_XPIPE_CLASSIFY:
        CTC_ERROR_RETURN(sys_usw_global_get_xpipe_classify(lchip, value));
        break;
    case CTC_GLOBAL_SID_EDIT_MODE:
        {
            *(uint32*)value = p_usw_register_master[lchip]->sid_edit_mode ? 0 : 1;
        }
        break;
   case CTC_GLOBAL_FORCE_STK_PARSER:
        cmd = DRV_IOR(IpeHeaderAdjustCtl_t, IpeHeaderAdjustCtl_forceSkipHeaderParser_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        *(bool*)value = field_val;
        break;
    case CTC_GLOBAL_MAX_HECMP_MEM:
        CTC_ERROR_RETURN(sys_usw_nh_get_max_hecmp(lchip, value));
        break;
    case CTC_GLOBAL_LB_HASH_GLOBAL_PROPERTY:
        CTC_ERROR_RETURN(_sys_usw_global_lb_hash_get_property(lchip, value));
        break;
    case CTC_GLOBAL_MAC_LIMIT_MODE:
        CTC_ERROR_RETURN(sys_usw_mac_limit_get_mode(lchip, &enable));
        *(uint32*)value = enable ? 1:0;
        break;
    case CTC_GLOBAL_DISCARD_IP_MARTIAN_ADDR_PKT:
        CTC_ERROR_RETURN(_sys_usw_global_get_martian_address(lchip, (ctc_global_martian_addr_t *)value));
        break;
    case CTC_GLOBAL_MAX_IPV4_ICMP_PKT_SIZE:
        cmd = DRV_IOR(IpeIntfMapperCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        if (DRV_FROM_TM(lchip))
        {
            field_val = GetIpeIntfMapperCtl(V, maxIpv4IcmpLength_f, ds);
        }
        else
        {
            field_val = GetIpeIntfMapperCtl(V, maxIcmpLength_f, ds);
        }
        *(uint32*)value = field_val;
        break;
    case CTC_GLOBAL_MAX_IPV6_ICMP_PKT_SIZE:
        cmd = DRV_IOR(IpeIntfMapperCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        if (DRV_FROM_TM(lchip))
        {
            field_val = GetIpeIntfMapperCtl(V, maxIpv6IcmpLength_f, ds);
        }
        else
        {
            field_val = GetIpeIntfMapperCtl(V, maxIcmpLength_f, ds);
        }
        *(uint32*)value = field_val;
        break;
    case CTC_GLOBAL_MIN_TCP_HDR_SIZE:
        cmd = DRV_IOR(ParserLayer4AppCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        field_val = GetParserLayer4AppCtl(V, tcpMinLength_f, ds);
        *(uint32*)value = field_val;
        break;
    case CTC_GLOBAL_DISCARD_TCP_FRAG_OFFSET_1_PKT:
        field_val = (*(bool*)value);
        cmd = DRV_IOR(ParserLayer4AppCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        field_val = GetParserLayer4AppCtl(V, tcpFragCheck_f, ds)&0x2;
        (*(bool*)value) = field_val?TRUE:FALSE;
        break;
    #if defined E_UNIT && (FEATURE_MODE == 0)
    case CTC_GLOBAL_NPM_IM_COLOR_HW_EN:
        if (DRV_FROM_AT(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        CTC_ERROR_RETURN(SYS_CB_RET(CTC_E_NOT_INIT, SYS_CB_NPM_IM_GET_ECPU_EN,lchip,value));
        break;
    #endif
    case CTC_GLOBAL_SCL_PAYLOAD_OFFSET_GRANU:
        if(DRV_FROM_TMM(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(IpeSclFlowCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        field_val = GetIpeSclFlowCtl(V, removeByteShift_f, ds);
        *(uint32*)value = field_val;
        break;
    case CTC_GLOBAL_ECO_EN:
        if (1 == SDK_WORK_PLATFORM)
        {
            return CTC_E_NOT_SUPPORT;
        }
        if(DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOR(CtcBufStoreProcTopCtlModuleEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            if (!GetCtcBufStoreProcTopCtlModuleEnable(V, enClkBufStoreErmDp0_f, ds))
            {
                CTC_SET_FLAG(field_val, CTC_GLOBAL_ECO_HIBERNATE);
            }
            else
            {
                if (!GetCtcBufStoreProcTopCtlModuleEnable(V, enClkMdio0_f, ds))
                {
                    CTC_SET_FLAG(field_val, CTC_GLOBAL_ECO_MDIO);
                }
                if (!GetCtcBufStoreProcTopCtlModuleEnable(V, enClkLed_f, ds))
                {
                    CTC_SET_FLAG(field_val, CTC_GLOBAL_ECO_LED);
                }
                cmd = DRV_IOR(CtcMiscCtlModuleEn_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
                if (!GetCtcMiscCtlModuleEn(V, enClkMcu_f, ds))
                {
                    CTC_SET_FLAG(field_val, CTC_GLOBAL_ECO_MCU);
                }

                cmd = DRV_IOR(GpioEnClk_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
                if (!GetGpioEnClk(V, cfgGpioEnClk_f, ds))
                {
                    CTC_SET_FLAG(field_val, CTC_GLOBAL_ECO_GPIO);
                }

                cmd = DRV_IOR(SupEnClk_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
                if (!GetSupEnClk(V, cfgEnClkI2CMaster0_f, ds))
                {
                    CTC_SET_FLAG(field_val, CTC_GLOBAL_ECO_I2C);
                }
            }
        }
        else
        {
            cmd = DRV_IOR(CtcMiscCtlClkEn_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
            if (!GetCtcMiscCtlClkEn(V, enClkOamEngine_f, ds))
            {
                CTC_SET_FLAG(field_val, CTC_GLOBAL_ECO_HIBERNATE);
            }
            else
            {
                if (!GetCtcMiscCtlClkEn(V, enClkMdio0_f, ds))
                {
                    CTC_SET_FLAG(field_val, CTC_GLOBAL_ECO_MDIO);
                }
                if (!GetCtcMiscCtlClkEn(V, enClkOobFc_f, ds))
                {
                    CTC_SET_FLAG(field_val, CTC_GLOBAL_ECO_OOBFC);
                }
                if (!GetCtcMiscCtlClkEn(V, enClkLed0_f, ds))
                {
                    CTC_SET_FLAG(field_val, CTC_GLOBAL_ECO_LED);
                }
                if (!GetCtcMiscCtlClkEn(V, enClkMcu_f, ds))
                {
                    CTC_SET_FLAG(field_val, CTC_GLOBAL_ECO_MCU);
                }
            }
        }

        *(uint32*)value = field_val;
        break;
    case CTC_GLOBAL_TRUNCATION_LEN_PROFILE:
        {
            uint8  shift = 0;
            uint8  length = 0;
            DsTruncationProfile_m truncation_prof;
            ctc_truncation_len_t* p_truncation_len = (ctc_truncation_len_t*)value;

            CTC_MAX_VALUE_CHECK(p_truncation_len->profile_id, SYS_TRUNCATION_PROFILE_MAX - 1);

            cmd = DRV_IOR(DsTruncationProfile_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, p_truncation_len->profile_id, cmd, &truncation_prof));
            shift = GetDsTruncationProfile(V, lengthShift_f, &truncation_prof);
            length = GetDsTruncationProfile(V, length_f, &truncation_prof);
            if ((DRV_IS_TMM(lchip) && (SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_C)) || DRV_IS_TMG(lchip))
            {
                p_truncation_len->truncated_len = (length << shift) & MCHIP_CAP(SYS_CAP_PKT_TRUNCATED_LEN);
            }
            else
            {
                p_truncation_len->truncated_len = length << shift;
            }
        }
        break;
    case CTC_GLOBAL_TRUNCATION_LEN:
        {
            cmd = DRV_IOR(EpeHeaderEditTruncationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &truncationctl));
            field_val = GetEpeHeaderEditTruncationCtl(V, cfgTruncationLen_f, &truncationctl);
            *(uint32*)value = field_val;
        }
        break;
    case CTC_GLOBAL_TRUNCATION_MODE:
        {
            uint8 mode;
            cmd = DRV_IOR(EpeHeaderEditTruncationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &truncationctl));
            mode = GetEpeHeaderEditTruncationCtl(V, cfgTruncationMode_f, &truncationctl);
            switch(mode)
            {
                case 1:
                    field_val = CTC_TRUNCATION_MODE_1;
                    break;
                case 3:
                    field_val = CTC_TRUNCATION_MODE_2;
                    break;
                default:
                    field_val = mode;
                    break;
            }
            *(uint32*)value = field_val;
        }
        break;
    case CTC_GLOBAL_MACDA_HIT_AGING_EN:
        {
            FibEngineLookupResultCtl_m lookupResultCtl;
            uint32 ctl_bmp = 0;
            cmd = DRV_IOR(FibEngineLookupResultCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lookupResultCtl));
            field_val = GetFibEngineLookupResultCtl(V, gMacDaLookupResultCtl_agingEn_f,&lookupResultCtl);
            ctl_bmp = field_val ? GetFibEngineLookupResultCtl(V, daAgingControlBit_f,&lookupResultCtl) : 0;
            *(uint32*)value = field_val ? (ctl_bmp == 0x01 ? 2 : (ctl_bmp == 0x02 ? 3 : 1)) : 0;
        }
        break;
    case CTC_GLOBAL_LOOP_MODE:
        {
            uint8 mode = 0;
            if (((SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_A) && DRV_IS_TMM(lchip)) || DRV_IS_TMG(lchip))
            {
                return CTC_E_NOT_SUPPORT;
            }
            CTC_ERROR_RETURN(sys_usw_internal_port_get_loop_mode(lchip, &mode));
            *(uint32*)value = mode;
        }
        break;
    case CTC_GLOBAL_DECAPED_FORCE_IPMC:
        {
            IpePreLookupCtl_m ipe_pre_lkup;
            cmd = DRV_IOR(IpePreLookupCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_pre_lkup));

            field_val = GetIpePreLookupCtl(V, routeAfterDecapMcastEn_f, &ipe_pre_lkup);
            (*(uint32*)value) = field_val ? 1 : 0;
        }
        break;
    case CTC_GLOBAL_MCAST_LOGIC_REP_THRD:
        *(uint32 *)value = p_usw_register_master[lchip]->logic_rep_threshold;
        break;
    case CTC_GLOBAL_STATION_MOVE_MODE:
       *(uint32 *)value = p_usw_register_master[lchip]->station_move_mode;
       break;

    default:
        return CTC_E_NOT_SUPPORT;

    }


    return CTC_E_NONE;
}

int32
sys_usw_wb_sync_register_cb(uint8 lchip, uint8 module,uint8 entries, sys_wb_sync_fn fn)
{
    if (NULL == p_usw_register_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }

    CTC_MAX_VALUE_CHECK(module, CTC_FEATURE_MAX - 1);

    p_usw_register_master[lchip]->wb_sync_cb[module] = fn;
    p_usw_register_master[lchip]->wb_entries[module] = entries;

    return CTC_E_NONE;
}

int32
sys_usw_dump_db_register_cb(uint8 lchip, uint8 module, CTC_DUMP_MASTER_FUNC fn)
{
    if (NULL == p_usw_chip_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }

    CTC_MAX_VALUE_CHECK(module, CTC_FEATURE_MAX - 1);

    p_usw_chip_master[lchip]->dump_cb[module] = fn;

    return CTC_E_NONE;
}

int32
sys_usw_global_set_logic_destport_en(uint8 lchip, uint8 enable)
{
    uint32 cmd = 0;
    uint32 value = 0;

    if (NULL == p_usw_register_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }
    value = enable?1:0;
    cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_headerCarryLogicDestPort_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(EpeHdrAdjustCtl_t, EpeHdrAdjustCtl_headerCarryLogicDestPort_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(QMgrCtl_t, QMgrCtl_queueEntryCarryLogicDestPort_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(QMgrCtl_t, QMgrCtl_logicDestPort64kMode_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(QWriteCtl_t, QWriteCtl_queueEntryCarryLogicDestPort_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(QWriteCtl_t, QWriteCtl_logicDestPort64kMode_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(BufferRetrieveCtl_t, BufferRetrieveCtl_queueEntryCarryLogicDestPort_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOW(BufferStoreCtl_t, BufferStoreCtl_headerCarryLogicDestPort_f);
    SYS_SET_FIELD_TBL_ALL_DP(lchip, cmd, value);

    return CTC_E_NONE;
}

int32
sys_usw_global_get_logic_destport_en(uint8 lchip, uint8* enable)
{
    uint32 cmd = 0;
    uint32 value = 0;
    SYS_REGISTER_INIT_CHECK;
    cmd = DRV_IOR(BufferStoreCtl_t, BufferStoreCtl_headerCarryLogicDestPort_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    *enable = value;

    return CTC_E_NONE;
}
int32
sys_usw_global_set_gint_en(uint8 lchip, uint8 enable)
{
    if (NULL == p_usw_register_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }
    p_usw_register_master[lchip]->gint_en = enable? 1: 0;

    return CTC_E_NONE;
}

int32
sys_usw_global_get_gint_en(uint8 lchip, uint8* enable)
{
    if (NULL == p_usw_register_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }

    CTC_PTR_VALID_CHECK(enable);


    *enable = p_usw_register_master[lchip]->gint_en;

    return CTC_E_NONE;
}

int32
sys_usw_global_get_station_move_mode(uint8 lchip, uint8* enable)
{
    if (NULL == p_usw_register_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }
    CTC_PTR_VALID_CHECK(enable);
    
    *enable = p_usw_register_master[lchip]->station_move_mode;

    return CTC_E_NONE;
}


int32
sys_usw_global_set_xgpon_en(uint8 lchip, uint8 enable, uint8 mode)
{
    uint32 cmd = 0;
    uint32 value = 0;
    uint32 offset = 0;
    uint16 loop = 0;
    IpeBridgeCtl_m ipe_bridge_ctl;
    DsErmChannel_m erm_chan;
    BufRetrvReserved_m BufRetrvReserved;

    if (NULL == p_usw_register_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }

    if(2 == mode)
    {
        return CTC_E_NONE;/*no need enable xgpon*/
    }

    p_usw_register_master[lchip]->xgpon_en = enable? 1: 0;

    CTC_ERROR_RETURN(sys_usw_acl_set_global_cfg(lchip, 0, enable));     /*Gem port enable*/

    if (DRV_IS_DUET2(lchip))
    {
        value = enable?0:1;
        cmd = DRV_IOW(IpeLearningCtl_t, IpeLearningCtl_hwVsiMacLimitEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        value = enable?0:1;
        cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_categoryIdUse4W_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOR(IpeUserIdCtl_t, IpeUserIdCtl_macPortTypeMacSaFieldShareType_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        value = enable?(value|0x1):(value&0x2);
        cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_macPortTypeMacSaFieldShareType_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        value = enable?1:0;
        cmd = DRV_IOW(IpeLoopbackHeaderAdjustCtl_t, IpeLoopbackHeaderAdjustCtl_customerLabelMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        value = enable?1:0;
        cmd = DRV_IOW(IpeLearningCtl_t, IpeLearningCtl_srcMismatchDiscard_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        value = enable?1:0;
        cmd = DRV_IOW(IpeLearningCtl_t, IpeLearningCtl_srcMismatchDiscardException_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        value = enable?1:0;
        cmd = DRV_IOW(IpeLearningCtl_t, IpeLearningCtl_srcMismatchNoDiscardException_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        value = enable?1:0;
        cmd = DRV_IOW(IpeLearningCtl_t, IpeLearningCtl_srcMismatchException_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        value = enable?0:1;
        cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_discardMplsTagTtl0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        value = enable?0:1;
        cmd = DRV_IOW(FlowTcamLookupCtl_t, FlowTcamLookupCtl_coppKeyIpAddrShareType0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }

    if (DRV_FROM_TM(lchip))
    {
        value = enable?1:0;
        cmd = DRV_IOW(IpeLoopbackHeaderAdjustCtl_t, IpeLoopbackHeaderAdjustCtl_logicSrcPort64kMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(BufferStoreCtl_t, BufferStoreCtl_logicSrcPort64kMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_logicSrcPort64kMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(IpeAclQosCtl_t, IpeAclQosCtl_dot1AeFieldShareMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        value = 0;
        cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_ponAppEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(IpeBridgeCtl_t, IpeBridgeCtl_ponAppEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(FibAccelerationCtl_t, FibAccelerationCtl_ponAppEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(FibEngineLookupCtl_t, FibEngineLookupCtl_ponAppEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        value = enable?1:0;
        cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_gemPortRecoverEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_gemPortRecoverFromNexthopEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(EpeNextHopCtl_t, EpeNextHopCtl_nhpOuterEditReadValid_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        cmd = DRV_IOW(EpeHeaderEditCtl_t, EpeHeaderEditCtl_voltEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        /*set oun flex>onu>pon flex>pon*/
        value = enable?4:0;
        cmd = DRV_IOW(IpeUserIdCtl_t, IpeUserIdCtl_userIdResultPriorityMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        value = enable?0:1;
        cmd = DRV_IOW(IpeLearningCtl_t, IpeLearningCtl_hwVsiMacLimitEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        value = enable?1:0;
        cmd = DRV_IOW(IpeLearningCtl_t, IpeLearningCtl_stationMoveException_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        sal_memset(&ipe_bridge_ctl, 0, sizeof(IpeBridgeCtl_m));

        CTC_ERROR_RETURN(sys_usw_nh_get_resolved_offset(lchip, SYS_NH_RES_OFFSET_TYPE_BRIDGE_NH,
                                                                   &offset));
        cmd = DRV_IOR(IpeBridgeCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_bridge_ctl));
        SetIpeBridgeCtl(V, macDaPolicerControlBit_f, &ipe_bridge_ctl, 1);
        SetIpeBridgeCtl(V, ponNextHop_0_ponBypassIngressEdit_f, &ipe_bridge_ctl, 1);
        SetIpeBridgeCtl(V, ponNextHop_0_ponLengthAdjustType_f, &ipe_bridge_ctl, 0);
        SetIpeBridgeCtl(V, ponNextHop_0_ponNextHopExt_f, &ipe_bridge_ctl, 0);
        SetIpeBridgeCtl(V, ponNextHop_0_ponNextHopPtr_f, &ipe_bridge_ctl, offset);
        SetIpeBridgeCtl(V, ponNextHop_1_ponBypassIngressEdit_f, &ipe_bridge_ctl, 1);
        SetIpeBridgeCtl(V, ponNextHop_1_ponLengthAdjustType_f, &ipe_bridge_ctl, 0);
        SetIpeBridgeCtl(V, ponNextHop_1_ponNextHopExt_f, &ipe_bridge_ctl, 0);
        SetIpeBridgeCtl(V, ponNextHop_1_ponNextHopPtr_f, &ipe_bridge_ctl, offset);
        SetIpeBridgeCtl(V, macDaPolicerLevel_f, &ipe_bridge_ctl, 1);
        SetIpeBridgeCtl(V, macDaPolicerPhbEn_f, &ipe_bridge_ctl, 0);
        SetIpeBridgeCtl(V, policerPtr0SplitSupportEn_f, &ipe_bridge_ctl, 0);
        SetIpeBridgeCtl(V, policerPtr1SplitSupportEn_f, &ipe_bridge_ctl, 0);
        cmd = DRV_IOW(IpeBridgeCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_bridge_ctl));

        CTC_ERROR_RETURN(sys_usw_global_set_logic_destport_en(lchip, enable));

        if(DRV_FROM_TMM(lchip))
        {
            for (loop = 0; loop < MCHIP_CAP(SYS_CAP_CHANNEL_NUM); loop++)
            {
                if (!SYS_IS_NETWORK_CHANNEL(loop))
                {
                    continue;
                }
                cmd = DRV_IOR(DsErmChannel_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, loop, cmd, &erm_chan));
                SetDsErmChannel(V, ermProfId_f, &erm_chan, 7); /*SYS_ERM_PROFILE_NH_GROUP*/
                cmd = DRV_IOW(DsErmChannel_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, loop, cmd, &erm_chan));
            }
        }
    }
    cmd = DRV_IOR(EpeHeaderEditCtl_t, EpeHeaderEditCtl_intEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    if (enable)
    {
        p_usw_register_master[lchip]->int_en = value? 1: 0;
        value = 0;
    }
    else
    {
        value = p_usw_register_master[lchip]->int_en;
    }
    cmd = DRV_IOW(EpeHeaderEditCtl_t, EpeHeaderEditCtl_intEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    cmd = DRV_IOR(QWriteCtl_t, QWriteCtl_tempQMsgInfoType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    if (enable)
    {
        p_usw_register_master[lchip]->qmsg_info_type = value;
        value = 1;
    }
    else
    {
        value = p_usw_register_master[lchip]->qmsg_info_type;
    }
    cmd = DRV_IOW(EpeHdrAdjustCtl_t, EpeHdrAdjustCtl_tempQMsgInfoType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    cmd = DRV_IOW(QWriteCtl_t, QWriteCtl_tempQMsgInfoType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    if ((SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) && DRV_IS_TSINGMA(lchip))
    {
        value = enable?0:1;
        cmd = DRV_IOW(IpePktProcReserved_t, IpePktProcReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }

    if (DRV_IS_TSINGMA(lchip))
    {
        sal_memset(&BufRetrvReserved, 0, sizeof(BufRetrvReserved_m));
        cmd = DRV_IOR(BufRetrvReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &BufRetrvReserved));
        value = GetBufRetrvReserved(V, reserved_f, &BufRetrvReserved);
        value &= ~(1<<0);
        SetBufRetrvReserved(V, reserved_f, &BufRetrvReserved, value);
        cmd = DRV_IOW(BufRetrvReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &BufRetrvReserved));
    }

    return CTC_E_NONE;
}

int32
sys_usw_global_get_xgpon_en(uint8 lchip, uint8* enable)
{
    if (NULL == p_usw_register_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }
    CTC_PTR_VALID_CHECK(enable);


    *enable = p_usw_register_master[lchip]->xgpon_en;

    return CTC_E_NONE;
}

int32
sys_usw_global_set_int_en(uint8 lchip, uint8 enable)
{
    if (NULL == p_usw_register_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }
    p_usw_register_master[lchip]->int_en = enable? 1: 0;

    return CTC_E_NONE;
}

int32
sys_usw_global_get_int_en(uint8 lchip, uint8* enable)
{
    if (NULL == p_usw_register_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }
    CTC_PTR_VALID_CHECK(enable);


    *enable = p_usw_register_master[lchip]->int_en;

    return CTC_E_NONE;
}

int32
sys_usw_global_get_flow_record_en(uint8 lchip, uint8* enable)
{
    CTC_PTR_VALID_CHECK(enable);
    if (NULL == p_usw_register_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }
    *enable = p_usw_register_master[lchip]->flow_record_en;
    return CTC_E_NONE;
}

int32
sys_usw_register_get_truncation_profile_id(uint8 lchip, uint32 length, uint8 size, uint8* profile_id)
{
    int32 ret = CTC_E_NONE;
    uint8 shift = 0;
    uint8 len = 0;
    uint8 loop = 0;
    uint8 find = 0;
    uint16 profile_len = 0;
    uint16 profile_len_min = MCHIP_CAP(SYS_CAP_PKT_TRUNCATED_LEN);
    uint32 cmd = 0;
    uint32 value = 0;
    DsTruncationProfile_m truncation_prof;

    SYS_REGISTER_INIT_CHECK;
    CTC_PTR_VALID_CHECK(profile_id);
    SYS_USW_REGISTER_LOCK(lchip);

    /*if highest bit set, indicate config by profile id, else config by length*/
    if(CTC_IS_BIT_SET(length, (size - 1)))
    {
        value = CTC_BIT_UNSET(length, (size - 1));
        if(value > (SYS_TRUNCATION_PROFILE_MAX - 1))
        {
            CTC_ERROR_GOTO(CTC_E_INVALID_PARAM, ret, OUT);
        }
        *profile_id = value;
    }
    else
    {
        for (loop = 0; loop < SYS_TRUNCATION_PROFILE_MAX; loop++)
        {
            cmd = DRV_IOR(DsTruncationProfile_t, DRV_ENTRY_FLAG);
            CTC_ERROR_GOTO(DRV_IOCTL(lchip, loop, cmd, &truncation_prof), ret, OUT);

            shift = GetDsTruncationProfile(V, lengthShift_f, &truncation_prof);
            len = GetDsTruncationProfile(V, length_f, &truncation_prof);
            profile_len = len << shift;
            if ((DRV_IS_TMM(lchip) && (SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_C)) || DRV_IS_TMG(lchip))
            {
                /*TM.MX vesion 2 truncation len must less than 1024*/
                profile_len &= 0x3FF;
            }
            if (profile_len >= length && profile_len <= profile_len_min)
            {
                find = 1;
                *profile_id = loop;
                profile_len_min = profile_len;
            }
        }

        if(!find)
        {
            CTC_ERROR_GOTO(CTC_E_INVALID_PARAM, ret, OUT);
        }
    }
OUT:
    SYS_USW_REGISTER_UNLOCK(lchip);
    return ret;
}

int32
sys_usw_global_failover_en(uint8 lchip, uint32 enable)
{
    uint32 cmd = 0;
    uint32 value = 0;

    value = enable?1:0;
    SYS_REGISTER_INIT_CHECK;
    /* linkagg failover */
    cmd = DRV_IOW(LagEngineCtl_t, LagEngineCtl_linkChangeEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    /* aps failover aps */
    cmd = DRV_IOW(MetFifoCtl_t, MetFifoCtl_linkChangeEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    return CTC_E_NONE;
}

void
sys_usw_register_wb_sync_all(uint8 lchip)
{
    uint8 mod_id = 0,sub_id =0;
    uint32 sync_bmp = 0;

    for (mod_id = 0; mod_id < CTC_FEATURE_MAX; mod_id++)
    {
        sync_bmp = ctc_wb_get_sync_bmp(lchip, mod_id);
        if (!sync_bmp )
        {
            continue;
        }

        for (sub_id = 0; sub_id <p_usw_register_master[lchip]->wb_entries[mod_id]; sub_id++)
        {
            if (!CTC_IS_BIT_SET(sync_bmp, sub_id) )
            {
                continue;
            }

            if (p_usw_register_master[lchip]->wb_sync_cb[mod_id])
            {
                p_usw_register_master[lchip]->wb_sync_cb[mod_id](lchip,(mod_id <<8 | sub_id));
            }
        }
    }
}

STATIC void
_sys_usw_register_wb_timer_handler(void* arg)
{
    uint8 lchip =  (uintptr)arg;
    uint8 mod_id = 0, sub_id = 0;
    uint8 pp_id = 0;
    uint32 app_id;
    uint32 sync_bmp = 0;
    uint8 time_up = 0;
    sal_systime_t timer_now;
    sal_systime_t* tv1;
    sal_systime_t* tv2;

    if(!p_usw_register_master[lchip])
        return;

    for (mod_id = 0; mod_id < CTC_FEATURE_MAX; mod_id++)
    {
        SYS_FEATURE_PP_LOOP_START(lchip, mod_id, pp_id)
        sync_bmp = ctc_wb_get_sync_bmp(lchip+pp_id, mod_id);
        if (!sync_bmp )
        {
            continue;
        }
        sal_gettime(&timer_now);
        tv1 = &(p_usw_register_master[lchip]->wb_last_time[mod_id+pp_id*CTC_FEATURE_MAX]);
        tv2 = &(timer_now);

        if(tv2->tv_usec >= tv1->tv_usec)
        {
            time_up = ( ((tv2->tv_sec - tv1->tv_sec)*1000 + (tv2->tv_usec - tv1->tv_usec)/1000) >= p_usw_register_master[lchip]->wb_interval);
        }
        else
        {
            time_up = ( ((tv2->tv_sec - tv1->tv_sec - 1)*1000 + (tv2->tv_usec + 1000000 - tv1->tv_usec)/1000) >= p_usw_register_master[lchip]->wb_interval);
        }
        if ( !time_up)
        {
            continue;
        }
        for (sub_id = 0; sub_id <p_usw_register_master[lchip]->wb_entries[mod_id]; sub_id++)
        {
            if (!CTC_IS_BIT_SET(sync_bmp, sub_id) )
            {
                continue;
            }

            app_id = mod_id <<8 | sub_id;
            if (p_usw_register_master[lchip]->wb_sync_cb[mod_id])
            {
                if(p_usw_register_master[lchip]->wb_sync_cb[mod_id](lchip+pp_id,app_id))
                {
                   CTC_WB_DBG_OUT(CTC_DEBUG_LEVEL_ERROR,"sync error happen! mod_id : %d, sub_id : %d.\n",mod_id,sub_id);
                   return;
                }
            }
        }
        SYS_FEATURE_PP_LOOP_END(pp_id)
    }
}

void sys_usw_register_wb_updata_time(uint8 lchip,uint8 mod_id, uint8 enable)
{
    uint8 pp_id = lchip - drv_vchip_get_pp_base(lchip);
    if(p_usw_register_master[lchip] && enable)
    {
        sal_gettime(&p_usw_register_master[lchip]->wb_last_time[mod_id + pp_id * CTC_FEATURE_MAX]);
    }
    return;
}

int32
sys_usw_register_wb_sync_timer_en(uint8 lchip, uint8 enable)
{
    int32 ret = 0;
    uintptr lchip_tmp = lchip;
    if(!p_usw_register_master[lchip] || !CTC_WB_DM_MODE(lchip))
    {
        return CTC_E_INVALID_PTR;
    }

    p_usw_register_master[lchip]->wb_timer_en = enable;

    if ( p_usw_register_master[lchip]->wb_timer_en )
    {
        if (!p_usw_register_master[lchip]->wb_timer)
        {
            ret = sal_timer_create(&p_usw_register_master[lchip]->wb_timer, _sys_usw_register_wb_timer_handler, (void*)lchip_tmp);
            if (0 != ret)
            {
                SYS_REGISTER_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "sal_timer_create failed  0x%x\n", ret);
                return ret ;
            }
        }
        else
        {
            sal_timer_stop(p_usw_register_master[lchip]->wb_timer);
        }
         sal_timer_start(p_usw_register_master[lchip]->wb_timer, p_usw_register_master[lchip]->wb_interval);
    }
    else
    {
        if (p_usw_register_master[lchip]->wb_timer)
        {
            sal_timer_stop(p_usw_register_master[lchip]->wb_timer);
            sal_timer_destroy(p_usw_register_master[lchip]->wb_timer);
            p_usw_register_master[lchip]->wb_timer = NULL;
        }
    }
    return CTC_E_NONE;

}

const char*
sys_usw_register_get_reason_desc(uint8 lchip, uint16 reason_id)
{
    static char reason_desc[CTC_DIAG_REASON_DESC_LEN] = {0};
    switch (reason_id)
    {
    case CTC_DROP_NONE                           :
        return "None drop";
    case CTC_DROP_LPBK_ERR                       :
        return "Loopback error";
    case CTC_DROP_PARSER_ERR                     :
        return "Parser error";
    case CTC_DROP_EXCP                           :
        return "Exception config";
    case CTC_DROP_TRANSIT_DISABLE                :
        return "Transit disable";
    case CTC_DROP_RECEIVE_DISABLE                :
        return "Receive disable";
    case CTC_DROP_FWD_ERR                        :
        return "Destination check fail";
    case CTC_DROP_VLAN_FILTER                    :
        return "Vlan filtering";
    case CTC_DROP_IP_CHK                         :
        return "Ip address or packet check fail";
    case CTC_DROP_STP_CHK                        :
        return "Stp check fail";
    case CTC_DROP_POLICING                       :
        return "Exceed policer threshold";
    case CTC_DROP_SECURITY_CHK                   :
        return "Security check fail";
    case CTC_DROP_PORT_MAC_CHK                   :
        return "Port mac check fail";
    case CTC_DROP_ISOLATE_CHK                    :
        return "Port isolate check fail";
    case CTC_DROP_PKT_ERR                        :
        return "Packet check error";
    case CTC_DROP_HW_ERR                         :
        return "Hardware error";
    case CTC_DROP_STK_CHK                        :
        return "Stacking check fail";
    case CTC_DROP_BPE_PORT_ERR                   :
        return "BPE port configure error";
    case CTC_DROP_IP_SRC_GUARD                   :
        return "Ip source guard check fail";
    case CTC_DROP_LAG_EMPTY                      :
        return "Linkagg group no member";
    case CTC_DROP_APS                            :
        return "APS";
    case CTC_DROP_SCL_DENY                       :
        return "Scl deny";
    case CTC_DROP_ACL_DENY                       :
        return "Acl deny";
    case CTC_DROP_PTP                            :
        return "Ptp packet or config error";
    case CTC_DROP_OAM                            :
        return "Oam packet or config error";
    case CTC_DROP_DOT1AE                         :
        return "Dot1ae packet or config error";
    case CTC_DROP_MIMICRY                        :
        return "Mimicry error";
    case CTC_DROP_VPLS                           :
        return "Vpls packet or config error";
    case CTC_DROP_MIRROR                         :
        return "Mirror config error";
    case CTC_DROP_TRILL                          :
        return "Trill packet or config error";
    case CTC_DROP_BFD                            :
        return "Bfd packet or config error";
    case CTC_DROP_PON                            :
        return "PON error";
    case CTC_DROP_ARP_OR_DHCP_ERR                :
        return "ARP or DHCP packet check fail";
    case CTC_DROP_ARP_MISS                       :
        return "Arp miss";
    case CTC_DROP_VXLAN_CHK                      :
        return "Vxlan check fail";
    case CTC_DROP_TUNNEL_CHK                     :
        return "Tunnel check fail";
    case CTC_DROP_ICMP_ERR                       :
        return "Icmp packet or congfig error";
    case CTC_DROP_TTL_CHK                        :
        return "TTL check fail";
    case CTC_DROP_SD_CHK                         :
        return "Signal degradation";
    case CTC_DROP_MPLS_CHK                       :
        return "Mpls check fail";
    case CTC_DROP_MTU_CHK                        :
        return "Mtu check fail";
    case CTC_DROP_PLD_OP_ERR                     :
        return "Packet payload operation error";
    case CTC_DROP_LATENCY                        :
        return "Latency check fail";
    case CTC_DROP_EDIT_ERR                       :
        return "Next hop edit error";
    case CTC_DROP_CHKSUM_ERR                     :
        return "Checksum error";
    case CTC_DROP_TRAFFIC_MANAGER                :
        return "Trafic manager check fail";
    case CTC_DROP_NET_TX                         :
        return "Nettx check fail";
    case CTC_DROP_NET_RX                         :
        return "Netrx check fail";
    case CTC_DROP_QUEUE                          :
        return "Queue drop";
    case CTC_DROP_BS                             :
        return "Buffer store drop";
    case CTC_DROP_OTHER                          :
        return "Other drop reason";
    default:
        sal_sprintf(reason_desc, "Reason id:%d", reason_id);
        return reason_desc;
    }
}

